适用于低k介电层间器件的堆叠芯片SiP技术

Y. Matsuura, A. Watanabe, S. Kawakami
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引用次数: 5

摘要

本文提出了一种适用于低k层间介电介质“低k ILD”器件的堆叠芯片SiP技术。随着低k ILD器件数量的增加,它们也开始用于堆叠芯片SiP。然而,已知低k ILD材料具有易碎特性。结合手机等产品中使用的堆叠式SiP芯片在尺寸和高度上都有限制,由于封装结构复杂,芯片厚度需要薄,因此关注对低k ILD器件的影响是非常重要的。为了开发这种类型的堆叠芯片SiP,我们研究并重点研究了两个主题。一是在装配过程中如何控制模具上的热应力和机械应力。二是如何消除低k ILD中的裂缝。在第一个问题上,研究了合适的封装结构,以最大限度地减少低k ILD器件的应力,结果表明,低k ILD放置在堆叠模具顶部的器件结构是最好的。然而,这在低k ILD设备上有一个悬架。因此,由于在金属键合过程中模具受到压力,因此存在损坏低k ILD器件的风险。因此,我们提前通过在模具上的键合载荷模拟应力来检查线的键合条件,并从那里建立了合适的线的键合工艺。在第二个问题上,切割过程使模具暴露于裂纹起裂点的产生。经过评价,激光沟槽切割的新工艺可以有效地控制大应力器件产生裂纹的可能性。因此,根据包装结构、包装类型等将这个新流程应用于产品。最后,对批量生产的实物样品进行了可靠性测试,并通过了测试。因此,采用低k ILD技术的薄器件的堆叠芯片SiP已经建立
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Stacked die SiP technology suitable for devices with low-k inter-layer dielectric
This paper presents the stacked die SiP technology suitable for the devices with low-k inter-layer dielectric "low-k ILD". As devices with low-k ILD increase in number, they have also come to be used in stacked die SiP. The low-k ILD material is however, known to have a fragile characteristic. Combined with the stacked die SiP which has a limitation in die size and height for use in cellular phones and the like, it is very important to care about the influence on the device with low-k ILD because package structure is complex and the die thickness needs to be thin. To develop this type of stacked die SiP, we investigated and focused on two subjects. One was, how to control the thermal and mechanical stress on the die in the assembly. The other was, how eliminate cracks in the low-k ILD. On the first subject, the suitable package structure was examined to minimize the stress on the device with low-k ILD, and the result was that the structure of the device with low-k ILD placed the top of the stacked dies is the best. However, this has an overhang on the device with low-k ILD. There is therefore a risk of damaging the device with low-k ILD as the die is stressed during the wire bonding process. We therefore examined wire bonding conditions with simulation of stress by the bonding load on the die in advance, and from there, established the suitable wire bonding process. On the second subject, the dicing process exposes the die to the generation of crack initiation points. After the evaluation, the new dicing process with the laser groove dicing was effective in controlling possibilities of crack occurrence in devices experiencing large stress. Thus, this new process is applied to the product depending on a package structure, a package type, and so on. Finally, samples of real products in mass production were put through reliability tests and they passed. Stacked die SiP for thin devices with low-k ILD technology has therefore been established
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