Y. Liu, D. Desbiens, S. Irving, T. Luk, C. Lolar, Yumin Liu, Qiuxiao Qian
{"title":"Systematic evaluation of die thinning application in a power SIPs by simulation","authors":"Y. Liu, D. Desbiens, S. Irving, T. Luk, C. Lolar, Yumin Liu, Qiuxiao Qian","doi":"10.1109/ECTC.2006.1645773","DOIUrl":null,"url":null,"abstract":"In this paper, a lead frame based system in package (SIP) for power management is examined. This package is built using multiple die types including power IGBTs, diodes, and IC controllers. To maximize product performance the power components use an ultra thin back grind. Thin dies minimize RDS(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. However, the ultra thin die could be a potential risk for die cracking if it is done without careful evaluation, especially for die thickness as thin as 90 mum and 50 mum. So it is critical to understand the impact of thinning dies on the reliability of the product in assembly manufacture and vary reliability tests. Modeling and simulation with a smaller amount of empirical testing is a good way to evaluate this thin die application quickly and at a lower cost. Therefore, the objective of this paper is to fully investigate the thin die application in a power SIP with systematic simulation and analysis before real application. A large complicated and advanced 3D FEA model framework is developed for the SIP. The major modeling and evaluation work is categorized into two areas: One is to check the impact of the thin die on different assembly processes. The other is to simulate the major reliability tests such as temperature cycle (TMCL) and component-level reflow process. Comprehensive evaluation and analysis of the modeling and simulation results for the thin die application to a Fairchild power SIP are presented","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"56th Electronic Components and Technology Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2006.1645773","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
In this paper, a lead frame based system in package (SIP) for power management is examined. This package is built using multiple die types including power IGBTs, diodes, and IC controllers. To maximize product performance the power components use an ultra thin back grind. Thin dies minimize RDS(on), maximize thermal performance, and minimize the board standoff height by allowing the package to be thinner. However, the ultra thin die could be a potential risk for die cracking if it is done without careful evaluation, especially for die thickness as thin as 90 mum and 50 mum. So it is critical to understand the impact of thinning dies on the reliability of the product in assembly manufacture and vary reliability tests. Modeling and simulation with a smaller amount of empirical testing is a good way to evaluate this thin die application quickly and at a lower cost. Therefore, the objective of this paper is to fully investigate the thin die application in a power SIP with systematic simulation and analysis before real application. A large complicated and advanced 3D FEA model framework is developed for the SIP. The major modeling and evaluation work is categorized into two areas: One is to check the impact of the thin die on different assembly processes. The other is to simulate the major reliability tests such as temperature cycle (TMCL) and component-level reflow process. Comprehensive evaluation and analysis of the modeling and simulation results for the thin die application to a Fairchild power SIP are presented
本文研究了一种基于引线框架的封装电源管理系统(SIP)。该封装使用多种芯片类型构建,包括功率igbt、二极管和IC控制器。为了最大限度地提高产品性能,电源组件使用超薄背磨。薄模具最大限度地减少RDS(on),最大限度地提高热性能,并最大限度地减少板的高度,使封装更薄。然而,超薄模具可能是一个潜在的风险,模具开裂,如果没有仔细的评估,特别是模具厚度薄如90毫米和50毫米。因此,在装配制造和各种可靠性试验中,了解模具减薄对产品可靠性的影响是至关重要的。用少量的经验测试进行建模和仿真是快速评估这种薄模具应用的好方法,并且成本较低。因此,本文的目标是在实际应用之前,通过系统的仿真和分析,充分研究薄模具在功率SIP中的应用。开发了大型复杂先进的SIP三维有限元模型框架。主要的建模和评估工作分为两个方面:一是检查薄模具对不同装配工艺的影响。二是对温度循环(TMCL)和部件级回流过程等主要可靠性测试进行仿真。对该薄型模具应用于Fairchild power SIP的建模和仿真结果进行了综合评价和分析