56th Electronic Components and Technology Conference 2006最新文献_第5页

Effect of unfilled underfills on drop impact reliability performance of area array packages 未填充下填料对区域阵列封装跌落冲击可靠性性能的影响

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645687

E. Ibe, K. Loh, J. Luan, T. Y. Tee

引用次数: 10

The evolution of plastic deformation of Sn3.5Ag-based lead-free solders sn3.5 ag基无铅钎料的塑性变形演化

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645658

F. Gao, T. Takemoto

{"title":"The evolution of plastic deformation of Sn3.5Ag-based lead-free solders","authors":"F. Gao, T. Takemoto","doi":"10.1109/ECTC.2006.1645658","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645658","url":null,"abstract":"Small amount of additives, namely, 0.2Co + 0.1Ni, were doped into the Sn3.5Ag solder matrix which has been considered as one of the most promising candidates to replace the conventional Sn-Pb solders. The mechanical properties of the lead-free solders were assessed from the force-penetration curves measured by nanoindentation testing. These mechanical properties were then used as the input parameters in the simulation based on the Dao's method. In the meantime, the rate sensitivity value in the constitutive model, say sigma = Amiddotepsivdotm for the lead-free solders were also determined by the variable tensile speed methodology. The creep deformation of both solders is the function of the loading rate. The creep deformation behavior during nanoindentation testing at dwell time for Sn3.5Ag0.2Co0.1Ni solder seemed more severe than that for Sn3.5Ag solder. The pile-up phenomenon was more remarkable for Sn3.5Ag0.2Co0.1Ni solder. The simulated plastic deformation under indentation showed that the greatest plastic deformation was beneath the indentation tips for both of the solders. And the plastic deformation zone for Sn3.5Ag was slightly greater","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117031878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Three dimensional optical interconnect on organic circuit board 有机电路板上的三维光学互连

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645747

T. Matsubara, Keiko Oda, Kei-ichiro Watanabe, Kaori Tanaka, Maraki Maetani, Yuriko Nishimura, Shigeo Tanahashi

引用次数: 14

Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages 下填料圆角几何形状对有机倒装芯片封装中界面分层的影响

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645871

K. Kacker, S. Sidharth, A. Dubey, C. Zhai, R. Blish

{"title":"Impact of underfill fillet geometry on interfacial delamination in organic flip chip packages","authors":"K. Kacker, S. Sidharth, A. Dubey, C. Zhai, R. Blish","doi":"10.1109/ECTC.2006.1645871","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645871","url":null,"abstract":"Underfill delamination jeopardy in flip chip organic packages is driven by shear and peeling interfacial stresses, which are directly impacted by underfill fillet geometry. Finite element analysis (FEA) models were used to analyze the effect of underfill height and width on interfacial stresses in a typical organic flip chip package configuration. Peeling and shearing stresses were computed for a large combination of fillet heights and widths (15 times 16 = 240). Three locations of interest: die bottom corner/underfill, die edge/fillet top and fillet bottom/substrate, were studied. For each location, 3D surface plots were generated to depict the variation of shear/peel stress simultaneously with width and height. An analysis of variance (ANOVA) was conducted for the full factorial design of experiments (DOE) to quantify the effect of underfill fillet height and width on the numerically computed shear and peel stresses at each location. Interaction among these variables was permitted and studied, and was found to be significant in some cases. The dominant factor(s) governing interfacial stresses for each location was identified and optimum values recommended. Limited data, with corner fillet heights in the range ~2% to 70% of die thickness, suggested adequate reliability for most field applications. Additional data are required to further validate the results","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125986527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Mechanical modeling and analysis of board level drop test of electronic package 电子封装板位跌落试验的力学建模与分析

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645683

Junfeng Zhao, L. Garner

{"title":"Mechanical modeling and analysis of board level drop test of electronic package","authors":"Junfeng Zhao, L. Garner","doi":"10.1109/ECTC.2006.1645683","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645683","url":null,"abstract":"Solder joint reliability (SJR) issues caused by drop impact have received more and more attention from the industry in recent years. To assess the SJR in drop shock, electronic packages are generally surface mounted on a printed circuit board (PCB) whose oscillations subject the solder joint to alternating tensile and compressive loads. Many factors may affect solder joint performance in a drop test, such as the component position on the drop test board, the test board parameters (pad definition, solder resist opening, etc.) and the shock pulse. This increases the difficulties in mechanical analysis of these events. Drop testing becomes more challenging than ever as environment-friendly Pb-free solder material replaces Pb based solder. Pb-free solder has been noted (Luke et al, 2005) for increasing the risk in shock due to changes in elastic modulus and IMC strength. The failure mechanism of solder joint in drop test is also diverse. To understand all these phenomena, mechanical modeling and analysis is carried out in this paper. The modeling results have been calibrated through comparison with experiment results. Drop test based on the popular JEDEC (JESD22-B111) board were analyzed to understand the implication of this test to the electronic package. Several observations about the testing method are made, which aid in understanding the drop test results and observations are made as to how this test might be improved. A modeling design of experiment (DOE) was done to study the key structural parameters including solder ball height, package stiffness, package thickness, ball pattern and package dimension. These results are helpful in understanding the package and board design parameters to most impact drop test performance and allow for improved performance by design","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125995538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Reworkable no-flow underfilling for both tin-lead and lead-free reflows for CSP assembled under air 可用于在空气下组装的CSP的锡铅和无铅回流管的可修复的无流下填充

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645694

W. Yin, N. Lee

引用次数: 8

Design and characterization of an integrated passive balun for quad band GSM applications 用于四频带GSM应用的集成无源平衡器的设计和特性

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645700

J. Mondal, Li Li, J. Drye

{"title":"Design and characterization of an integrated passive balun for quad band GSM applications","authors":"J. Mondal, Li Li, J. Drye","doi":"10.1109/ECTC.2006.1645700","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645700","url":null,"abstract":"In today's mobile phone application, more functionality and integration are expected in the front end RF sections, which include transceiver module, PA module, power management, digital processors, and others. In addition, package and module size, and form factor become an important aspect for these handhold applications. In this paper, we report the successful design of a smaller size, low loss, and cost effective dual balun for cell, EGSM, DCS & PCS bands (quad band) GSM/EDGE applications. The designed balun can be implemented onto a transceiver module's transmit (Tx) path. The integrated passive device (IPD) baluns show superior performance to commercially available discrete SMT baluns, with a much smaller size. Viable packaging approach is also explored to keep the cost and size low with hardly any penalty to electrical performance. The final smaller size balun design reduces die size, and hence die cost without sacrificing the performance. The size of the quad band GSM balun is 1.2mmtimes1.4mm. Measured insertion loss (IL) and return loss (RL) of the balun for low band - Tx and high band - Tx show IL < 0.8 dB, RL < 12dB. Measured amplitude & phase balance for low band - Tx show amplitude balance < plusmn 0.02 dB, and phase balance < plusmn 0.1 deg. For high band - Tx, amplitude balance < plusmn 0.03 dB, phase balance < plusmn 0.2 deg","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129364459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Thermal effects of moisture inducing delamination in light-emitting diode packages 发光二极管封装中水分诱导分层的热效应

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1117/12.691555

Jianzheng Hu, Lianqiao Yang, M. Shin

引用次数: 28

Development of a novel deep silicon tapered via etch process for through-silicon interconnection in 3-D integrated systems 一种新型深硅锥形蚀刻工艺在三维集成系统中的应用

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645674

R. Nagarajan, L. Ebin, Lee Dayong, Soh Chee Seng, K. Prasad, N. Balasubramanian

引用次数: 38

Micro impact characterisation of solder joint for drop impact application 跌落冲击用焊点的微冲击特性

56th Electronic Components and Technology Conference 2006 Pub Date : 2006-07-05 DOI: 10.1109/ECTC.2006.1645627

E. Wong, Y. Mai, R. Rajoo, K. T. Tsai, F. Liu, S. Seah, Chang-Lin Yeh

引用次数: 33