Mechanical modeling and analysis of board level drop test of electronic package

Solder joint reliability (SJR) issues caused by drop impact have received more and more attention from the industry in recent years. To assess the SJR in drop shock, electronic packages are generally surface mounted on a printed circuit board (PCB) whose oscillations subject the solder joint to alternating tensile and compressive loads. Many factors may affect solder joint performance in a drop test, such as the component position on the drop test board, the test board parameters (pad definition, solder resist opening, etc.) and the shock pulse. This increases the difficulties in mechanical analysis of these events. Drop testing becomes more challenging than ever as environment-friendly Pb-free solder material replaces Pb based solder. Pb-free solder has been noted (Luke et al, 2005) for increasing the risk in shock due to changes in elastic modulus and IMC strength. The failure mechanism of solder joint in drop test is also diverse. To understand all these phenomena, mechanical modeling and analysis is carried out in this paper. The modeling results have been calibrated through comparison with experiment results. Drop test based on the popular JEDEC (JESD22-B111) board were analyzed to understand the implication of this test to the electronic package. Several observations about the testing method are made, which aid in understanding the drop test results and observations are made as to how this test might be improved. A modeling design of experiment (DOE) was done to study the key structural parameters including solder ball height, package stiffness, package thickness, ball pattern and package dimension. These results are helpful in understanding the package and board design parameters to most impact drop test performance and allow for improved performance by design