56th Electronic Components and Technology Conference 2006最新文献

{"title":"Fabrication of high aspect ratio 35 /spl mu/m pitch interconnects for next generation 3-D wafer level packaging by through-wafer copper electroplating","authors":"P. Dixit, J. Miao","doi":"10.1109/ECTC.2006.1645675","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645675","url":null,"abstract":"3-D wafer level packaging is one of the key technologies to fabricate next generation compact, highly dense and high speed electronic devices. In order to realize these future nanoscale IC devices, fabrication of through-wafer interconnects with ultra fine pitch, is the foremost requirement. High aspect ratio through-wafer interconnects connect several devices in vertical axis and thus offer the shortest possible interconnection length. Due to the shortest interconnect length, parasitic losses and time delay during signal propagation is the minimum, which result in faster speed. In this paper, we report the fabrication of very high aspect ratio (~15) ultra fine pitch (-35 mum) through-wafer copper interconnects by innovative electroplating process. In this technique, process parameters are continuously varied as the electroplating process goes on. To reduce the chances of void formation and to ensure the complete wetting of via surface with copper electrolyte, hydrophilic nature of vias surface is increased. Copper interconnects having diameter as low as 15 mum and height as high as 400 mum have been fabricated by above technique. Vertically standing and smooth copper interconnects with very fine grains are obtained, which are characterized by SEM","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114617313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of DIG (direct immersion gold) as a new surface finishes for mobile applications","authors":"Dongwook Kim, P. Bhimaraj, N. Watts, Y. Isao, C. Kumar, Youren Xu","doi":"10.1109/ECTC.2006.1645656","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645656","url":null,"abstract":"DIG (direct immersion gold) is evaluated as an alternative surface finish solution to Ni/Au system for mobile electronics. Three key points are studied in this paper. First, Au capping layer optimization was studied. At least 0.14mum Au thickness is needed to prevent Cu out-diffusion and achieve reasonable assembly process window. Second, compared interfacial microstructures and morphologies of IMCs formed on DIG and Ni/Au surface finishes. DIG provide uniform IMC layer with no void, defect and Au-Sn intermetallic compounds (IMC). Finally, reliability and fracture modes were studied. SAC 405 performs better than eutectic Pb-Sn for the temperature cycling test. Crack in Pb-Sn + DIG system is initiated from interface of Cu6Sn5 and bulk solder and propagated to bulk solder while crack path of Pb-Sn + Electrolytic Ni/Au is interface of Au-Sn IMC and bulk solder. For drop test, SAC405 + DIG system has mix fracture modes of bulk and IMC brittle fracture while SAC405 + electrolytic Ni/Au has shows complete IMC fracture mode","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116740419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability studies of a through via silicon stacked module for 3D microsystem packaging","authors":"S. Yoon, D. Witarsa, S. Yak Long Lim, V. Ganesh, A. Viswanath, T. Chai, K. Navas, V. Kripesh","doi":"10.1109/ECTC.2006.1645847","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645847","url":null,"abstract":"In this study, two types of reliability tests are studied for silicon stacked module. One is for temperature cycle solder joint reliability. Another is for drop impact test. Test vehicles are fabricated using silicon fabrication processes such as SiO2 deposition, metal deposition, lithography, through via formation, copper plating and dry or wet etching. After flipchip die and silicon substrate fabrication, they are assembled by flipchip bonder. Daisy chains are formed between flipchip dies and each silicon substrates and resistance measurement is carried out with temperature cycle test (-40/125degC, 2cycles/hr). In case of drop test, the JESD recommended condition B (e.g. 1500 G, 0.5 millisecond duration, and half-sine pulse) is adopted. And in-situ monitoring is carried out to observe the failure during the drop test. Reliability results of through via silicon stacked module indicated that it passed 1000 cycles T/C and survived drop impact test","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117118062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal fatigue reliability modeling and analysis of BGA socket assembly in system board with preloaded use condition","authors":"Liping Zhu, M. Summers, R. Uppalapati, K. Clyne","doi":"10.1109/ECTC.2006.1645741","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645741","url":null,"abstract":"Heat sink (HS) as thermo-mechanical solution is widely used in modern electronic packaging system including mobile, desktop and server machines to improve and maintain system thermal performance by removing heat away from IC component such as flip chip ball grid array (FCBGA) package and BGA socket. With increased power dissipation need, heat sinks usually carry considerable amount of mass and preload over the components in order to have optimal thermal engagement during operation, which greatly impact reliability performance of BGA solder joint under various reliability tests. Thermal test data show that the most failure locations of BGA balls in BGA socket are located off the package corner that can not be predicted by using traditional strain or energy based metric. Therefore developing a predictive modeling tool with physics based metric in assessing reliability performance of preloaded BGA solder joint still remains a challenge. A nonlinear finite element model including BGA socket and preload heat sink was developed for both standard and system level boards to investigate preload effect on thermo-mechanical reliability performance. Numerical modeling results show that potential failure locations of BGA balls can be identified by maximum principal stress and be correlated well with thermal cyclic validation test. An advanced fatigue life model with mean stress effect and inelastic strain range is also proposed for calculation of initial fatigue life for BGA solder joint","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123222763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development challenges for ambient light sensor packages","authors":"Young-Gon Kim, N. Kelkar.","doi":"10.1109/ECTC.2006.1645748","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645748","url":null,"abstract":"Ambient light sensor (ALS) products are gaining popularity as one of the most effective solution for power management and display quality enhancement in electronic products and systems. The battery life for mobile phones, notebook computers, PDAs, and digital cameras can be extended significantly by automatic brightness control through ambient light sensor (ALS) feedback. A recent study shows that the display backlight represents one-third of the total battery drain in a notebook computer. It is also possible to achieve a more comfortable display quality with human eye-like sensing features. Automotive applications, room lighting, and advanced color sensing are other application areas for ALS that have been changing our daily life. Intersil has successfully developed ALS products with 5-, 6-, and 8-pin package configurations. A figure in the paper shows an example of an ALS product, EL7900, with a compact 5-pin QFN package format. EL7900 and ISL29000 are light-to-current optical sensors, integrating a photodiode and current amplifier for a simple current output sensor. Intersil has also developed light to digital output sensors in 8-pin packages, namely, ISL29001 and ISL29002, combining a photodiode, current amplifier, filter, ADC and an I2C output","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123707636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization","authors":"H. Gan, S. Wright, R. Polastre, L. P. Buchwalter, R. Horton, P. Andry, C. Patel, C. Tsang, J. Knickerbocker, E. Sprogis, A. Pavlova, S.K. Kang, K. Lee","doi":"10.1109/ECTC.2006.1645806","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645806","url":null,"abstract":"To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The effect of IMC microstructure of solder joint on the mechanical drop performance in SnxAgCu and SnAgCuX CSP package","authors":"Y. Lai, P.C. Chen, Chang-Lin Yeh, J. Lee","doi":"10.1109/ECTC.2006.1645926","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645926","url":null,"abstract":"With the RoHS deadline approaching by July 1, 2006, many manufacturers are aggressively eliminating the use of lead in consumer electronic products. However, the development of lead-free products requires close cooperation between end-product manufacturers and component manufacturers because metallurgies, resin materials, reflows conditions and moisture resistance will be influenced. The increase in reflow temperature is generally considered to be the most difficult issue associated to the conversion to SnAgCu solder interconnect. But right now the mechanical drop performance in SnAgCu solder joint has been becoming another attractive topic even being industry headache due to brittle characteristics of SnAgCu interconnect. In the study, one 14 times 14 lead free CSP BGA with 0.3 mm/0.5 mm ball diameter/pitch was adopted as test vehicle. The intermetallic compounds morphology evolution which can be generated when using SnxAgCu and SnAgCuX solder ball in combination with electrolytic NiAu-plated substrates was investigated during 150degC thermal aging, such as single layer SnNi IMC and complex layer SnNi/SnNiCu IMC in the interface through top and cross-section view, respectively. In addition, the intensity of plate-like Ag3Sn IMC formation in the SnxAgCu solder bulk from 1 to 4%Ag was observed by SEM as well. The CSP BGA package with above combination was assembled to PC boards with OSP finish using Sn3Ag0.5Cu solder paste under 245degC peak temperature reflow. The test vehicle assembled was subject to mechanical drop test following JESD22-B111 to evaluate the solder joint integrity after zero and 150degC/250hrs thermal aging. The effect of interfacial IMC morphology evolution and Ag3Sn intensity in solder bulk by x (Ag percentage) and X (forth element addition) on the mechanical drop performance is concluded. Furthermore, one approaching in IMC microstructure control to overcome SnAgCu drop concern will be presented","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121734656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Drop impact analysis of Sn-Ag-Cu solder joints using dynamic high-strain rate plastic strain as the impact damage driving force","authors":"J. Pang, F. Che","doi":"10.1109/ECTC.2006.1645625","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645625","url":null,"abstract":"Board-level drop reliability test and analysis requires dynamic characterization of high strain-rate properties of bulk solder and solder joint failure tests. Drop impact analysis of board-level dynamic response (ie: G-levels and board bending strains) and over-simplification of deformation response of solder joints (ie: assuming elastic stress criteria) can lead to wrong conclusions in the physics-of-failure understanding in drop impact tests. Solder joint failures during drop testing is a complex failure interaction process between low cycle impact fatigue crack growths versus brittle fracture of the intermetallic interfaces. During a drop test event, dynamic hardening causes the yield stress in the solder to rise several times above the nominal monotonic tensile test yield stress. The increase in dynamic strength in the solder joint can cause dynamic strain cycling in the solder material and lead to progressive low cycle impact drop fatigue failures. On the other hand, when the drop loading is excessive, impact failure strength of the intermetallic interface will result in brittle fracture of the solder joint. Impact test were conducted with a split Hopkinson pressure bar (SHPB) test system to study the dynamic response of bulk solder materials and impact failure of solder joint interfaces. Solder joint reliability characterization by drop impact test with clamped-clamped boundary condition were investigated for PBGA assembly with Sn-Ag-Cu solder. FEA modeling and simulation of drop impact were conducted considering different solder constitutive models such as elastic and strain rate dependent plastic model to investigate the effect of solder constitutive model on dynamic response in the solder joint. The important finding of this study is that the constitutive model used has a major impact on dynamic response of solder joint stress and strain results. It was expected that strain rate dependent plastic model gave better correlation results than the simple elastic model. This study also investigates the IMC effect on solder strain response subject to drop impact test simulation","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121064440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Grain features of SnAgCu solder and their effect on mechanical behaviour of micro-joints","authors":"J. Gong, Changqing Liu, P. Conway, V. Silberschmidt","doi":"10.1109/ECTC.2006.1645655","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645655","url":null,"abstract":"SnAgCu alloy, which promises compatible properties with Sn-Pb solder, has been identified as one of the most potential Lead-free solders for electronic interconnections. However, due to the miniaturization of solder joints, a micro-joint of this material contains only few grains. In this case, the mechanical behaviour of solder alloys shifts from the polycrystal-based to single-crystal based. Since P-Sn, the matrix of SnAgCu solder, has a contracted body-centred tetragonal structure, its grains are expected to have anisotropic properties, which are important, the reliability of a micro-joint. The present paper studies the inelastic anisotropic behaviour of this material. In order to analyse the effect of grain features, solder joints at different size are formed under the different cooling rate. An in-situ shear test is then performed to correlate the mechanical behavior of a joint to its microstructural features. The results show that the decrease in the joint's dimension results in the diminishment of the number of grains, and that the inelastic behaviour of SnAgCu grains is orientation-dependent","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122837076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Processing and performance of broadband integrated resistor structures on non-planar topologies in hermetic silicon enclosure with vertical micro vias","authors":"C. Greisen, R. Hauffe, L. Shiv, S. Weichel, H. Korth, A. Kilian, M. Heschel, J. Kuhmann","doi":"10.1109/ECTC.2006.1645860","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645860","url":null,"abstract":"We present the integration of thin film nickel-chromium (NiCr) resistors into a hermetic, 3D structured silicon packaging platform for wafer level sealing and demonstrate their performance as broadband passive components. Resistors on the cavity side walls can be designed by modeling the material deposition as a unidirectional flux","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122877927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}