H. Gan, S. Wright, R. Polastre, L. P. Buchwalter, R. Horton, P. Andry, C. Patel, C. Tsang, J. Knickerbocker, E. Sprogis, A. Pavlova, S.K. Kang, K. Lee
{"title":"用于下一代微系统的无铅微接头(50 /spl μ /m间距):制造,组装和表征","authors":"H. Gan, S. Wright, R. Polastre, L. P. Buchwalter, R. Horton, P. Andry, C. Patel, C. Tsang, J. Knickerbocker, E. Sprogis, A. Pavlova, S.K. Kang, K. Lee","doi":"10.1109/ECTC.2006.1645806","DOIUrl":null,"url":null,"abstract":"To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"57 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"43","resultStr":"{\"title\":\"Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization\",\"authors\":\"H. Gan, S. Wright, R. Polastre, L. P. Buchwalter, R. Horton, P. Andry, C. Patel, C. Tsang, J. Knickerbocker, E. Sprogis, A. Pavlova, S.K. Kang, K. Lee\",\"doi\":\"10.1109/ECTC.2006.1645806\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process\",\"PeriodicalId\":194969,\"journal\":{\"name\":\"56th Electronic Components and Technology Conference 2006\",\"volume\":\"57 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-07-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"43\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"56th Electronic Components and Technology Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECTC.2006.1645806\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"56th Electronic Components and Technology Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2006.1645806","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization
To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process