56th Electronic Components and Technology Conference 2006最新文献

{"title":"Basic study of proper global wiring structure for advanced system in package","authors":"Y. Iwata, S. Yasuda, R. Satoh, E. Morinaga","doi":"10.1109/ECTC.2006.1645840","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645840","url":null,"abstract":"This paper is investigated on the global wiring structure for next-generation SiP structure (target wire length =10mm, target frequency =10GHz, without repeater) by using electromagnetic analysis and simulation. Toward this target, we decide to attain signal attenuation smaller than -10dB at 30GHz (3rd harmonics). For this purpose, we propose that the attenuation of signal has been improved by making structure of global wiring into strip-line + coplanar structure. As a result, we find the condition (wire thickness and width 1.2 mum, distance between wires and insulator thickness 2.4 mum), which can transmit the signal (|S21| > -10dB, |S31|, |S 41| < -30dB at 30GHz). Furthermore, the feasible region among characteristic impedance, wire pitch and, attenuation of signal is made clear by using above results. This result means that moving of the global wirings on SiP with 10GHz digital signal from the device to the interposer circuit board will be needed in near future","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128511830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly compliant bonding material and structure for micro- and opto-electronic applications","authors":"E. Suhir, D. Ingman","doi":"10.1109/ECTC.2006.1645890","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645890","url":null,"abstract":"Based on the developed analytical stress model, we demonstrate that the employment of highly compliant materials and structures as bonding layers in bi-material assemblies (joints) can lead to a significant stress relief. The model indicates that the interfacial shearing stress in an adhesively bonded or a soldered assembly is inversely proportional to the square root of the interfacial compliance, and that in \"conventional\" bi-material assemblies (characterized by moderately compliant bonding layers), the interfacial compliance is due to both the bonding layer and the bonded components. However, in assemblies with highly compliant bonds, it is the bonding material only that provides the high and favorable interfacial compliance. We suggest that an appropriate nano-wire array (NWA) fabricated on one or both bonded components be used as a suitable compliant bond. Based on the developed predictive model, we demonstrate that the application of the NWA as a compliant attachment can lead to a significant, about two orders of magnitude, increase in the interfacial compliance. This leads to a reduction in the interfacial shearing stress of about an order of magnitude (compared to the bonded joints using \"conventional\" adhesives or solders). We suggest that one of the modifications of the newly developed nano-particle material (NPM) be used in addition to, or instead of a NWA, to increase the compliance of the bonding layer. A suitable combination of both the NWA and NPM could be employed to provide a highly compliant and a highly reliable bonding material and structure. In this case the NPM is used as an embedding material for the NWA. Since the NPM has extraordinary mechanical and environmental properties, and, in combination with the appropriate NWA, can make an extremely highly compliant and a highly reliable bond, we expect that the NPM and NWA, used independently or in combination, find a wide application in various bi- and multi-material assemblies employed in micro- and optoelectronics, and well beyond the \"high-tech\" area","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128696388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Predictive model for adhesion loss of molding compounds from exposure to humid environments","authors":"T. P. Ferguson, J. Qu","doi":"10.1109/ECTC.2006.1645841","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645841","url":null,"abstract":"While absorbed moisture poses a significant threat to the reliability of microelectronic assemblies, the role of moisture to the constitutive damage behavior of interfacial adhesion is not clear. There currently exists a lag in fundamental empirical data depicting the loss in interfacial adhesion as a function of moisture concentration. Given this lag in experimental data, even less effort has been spent developing predictive models that account for the effect of moisture on interfacial adhesion. This paper presents a systematic study conducted to better understand the fundamental science of moisture-induced degradation of interfacial adhesion. It is comprised of both experimental and modeling components of analysis. The experimental portion of this work characterizes the intrinsic interfacial adhesion loss from moisture and identifies the major energy dissipation mechanisms involved in the debonding process for an epoxy-metal bond. The analytical model is based on absorption theory and uses fracture mechanics to predict the loss in adhesion as a function of moisture content. Good agreement is obtained when comparing model predictions to experimental data","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"500 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116194329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimum VCO's for radiofrequency applications","authors":"N. Boughanmi, A. Kachouri, M. Samet","doi":"10.1109/ECTC.2006.1645897","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645897","url":null,"abstract":"This paper presents voltage controlled oscillator (VCO) circuit employing MOS transistors intended for integrated transceiver, in which full compensation of process parameters variations can be obtained. This is realized by fitting on chip capacitance of LC resonator. This capacitance is used for tuning of resonant frequency. VCO output frequency is tuned by on-chip p /n-well junction varactors. The circuit topology minimizes the amount of fixed parasitic capacitance in the tank circuit. The simulation results show that the proposed VCO can reach the frequency wished to the telecommunication application. Parameters from an industrial 0.35 mum CMOS process are used for simulations. The nominal operating frequency of these oscillators is 2.4 GHz. They are designed to be resistant to supply and temperature effects. This oscillator achieves the necessary temperature and supply independence while being tunable about 2.4 GHz. Using only 2.5V of power supply and IV of tuned voltage, the circuit shows a simulated single-output sensitivity of 565 ppm/degC at 27degC temperature and -0.47%/Volt at 2V","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121062978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 60GHz radio chipset fully-integrated in a low-cost packaging technology","authors":"U. Pfeiffer, J. Grzyb, D. Liu, B. Gaucher, T. Beukema, B. Floyd, S. Reynolds","doi":"10.1109/ECTC.2006.1645830","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645830","url":null,"abstract":"We present a cost-effective plastic packaging technology for a fully-integrated 60GHz radio, used for communication in the 60GHz ISM band. The chipset supports 1-3 Gbps directional links using a ASK or PSK modulation, or it can be used in 500Mbps-1Gbps omni-directional links using an OFDM modulation. The antenna is integrated inside of the package and does not require any high-frequency external connection. The fabrication process of a direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. Both packages are robust against variations of the electrical properties of standard plastic mold materials","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126839243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fullwave simulation and validation of a complex packaging structure","authors":"B. Archambeault, S. Connor, D. de Araujo, A. Ruehli, C. Schuster","doi":"10.1109/ECTC.2006.1645816","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645816","url":null,"abstract":"Most high data rate PCBs has many layers. Signals can change layers with many different configurations, and often have long stubs. All these options can have different effects on the signal, and need to be properly simulated. This paper describes the initial efforts to develop a strategy to properly analyze these complex structures by first modeling a simple via structure where a signal trace changes from one side of a reference plane to the other side of the same plane. No long via stubs are included initially. The complexity of the via structure is further increased by adding more metal layers, via stubs, and a return current via (at different distances from the signal via). Practical structures of increasing complexity are modeled such as those found in high-end servers and blade systems. The structures were simulated using a number of different simulation techniques: finite-difference time-domain (FDTD), partial element equivalent circuit (PEEC) as presented in A. E. Ruehli (1974), finite integration technique (FIT), and finite element method (FEM). It is widely accepted that if completely different simulation techniques are able to capture the proper physics of the problem and get the same results, then the simulation results are valid. Good agreement was obtained for all configurations","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126826724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of photosensitive film sidewall profile with different exposure wavelength and process characteristics of plating bump technology","authors":"J. Yu, R. Yu, T. Tai, D. Huang, W. Jau, J. Lin, H. Tong, K. Hsieh","doi":"10.1109/ECTC.2006.1645782","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645782","url":null,"abstract":"Wafer bumping is growing in importance with the increasing used of flip chip package. In this study, we tried to determine which factors at photosensitive film lithography process had an effect on photosensitive film sidewall profile. The analysis of the experiment indicates that different exposure wavelength between G,H and I line wavelength or exposure energy and DOF (deep of focus) can affect the photosensitive film sidewall angle and are significant to a 80 % level. The use of projection optics have the ability to focus the image as various depths (80 mum or greater) photosensitive films; this enables straighter sidewall angles and especially critical to control UBM CD (critical dimension) for plating bump process. The effect of photosensitive film scumming has a major concern on bump shear and reliability of wafer bump performance the well process control by lithography process will keep as lower yield loss of solder bump. The scanning electron microscopy (SEM) cross-section profile analysis was performed on the different via opening of photosensitive film with un-plated bump wafers and tries to figure out the process window and using optical microscope (OM) and EDX analyzed also show out observed results of scumming remainders. The best lithography procedure well control before solder plating deposition process is addressed to make the flip chip package success","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117033800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated passive design library for multilayer PCB","authors":"G. Carchon, K. Vaesen, Xiao Sun, S. Brebels, T. Imaoka, T. Sawai, Y. Inoue","doi":"10.1109/ECTC.2006.1645892","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645892","url":null,"abstract":"An integrated passives library for a 4-metal layer microstrip PCB-technology has been developed featuring scaleable models for microstrip transmission lines, striplines, discontinuities, integrated single and multi-layer inductors and integrated capacitors. Capacitor Q-factors around 50 are obtained with Q-factors being primarily dominated by the dielectric's loss tangent. Inductor Q-factors around 40 are obtained for single and multi-layer integrated inductors. Bandpass filters, lowpass filters, quadrature couplers and baluns have been designed for the 2.4GHz and 5.2GHz band with good performance. The influence of temperature on the RF performance of integrated inductors, capacitors and an integrated bandpass filter has been evaluated over the 5degC-115degC temperature range","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"891 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131578117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Moisture diffusion study in electronic packaging using molecular dynamic simulation","authors":"H. Fan, E. Chan, C. Wong, M. Yuen","doi":"10.1109/ECTC.2006.1645843","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645843","url":null,"abstract":"Moisture induced reliability concerns have been extensively studied in package design. Popcorning in plastic-encapsulated IC packages is a defect frequently occurring in solder reflow due to moisture penetration into the packages. Moisture diffusion has a detrimental effect on the epoxy/copper interfacial adhesion and drastically reduces the reliability of the encapsulated package. The present study is focused on the moisture diffusion in both the epoxy molding compound (EMC) and the EMC/Cu interface. In order to evaluate which is the dominating moisture transport mechanism at the interface, molecular dynamic (MD) models were built using the 'Materials studio' software. Based on the conditions of 85degC/85%RH in qualifying tests in humidity chamber, the amount of water molecules are assigned to the packing cells in the MD models. All the MD simulations were performed at a temperature of 85degC using the constant-pressure and temperature ensemble (NPT). Non-bond interactions cut-off distance of 1.5 nm with a smooth switching function was used in all simulations. The simulation in each case study was performed with an interval of 1 femto second (fs) in each MD simulation step. The mean squared displacements of all water molecules were evaluated in each time-step to track the motion of the molecules. Constants of moisture diffusion in both bulk EMC material and EMC/Cu interface can be derived from the mean squared displacements. The MD results show that the value of the moisture diffusion coefficient at the EMC/Cu interface is higher than that in the bulk EMC material. It revealed that moisture can easily penetrate along the EMC/Cu interface. The MD simulation study has demonstrated that the seepage along the interface is the dominant mechanism for moisture diffusion into the EMC/Cu interface in plastic packages. This widely studied mechanism of moisture diffusion via the bulk EMC is an apparent a secondary moisture penetration path to the interface","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132961758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual die Pentium D package technology development","authors":"M. Manusharow, A. Hasan, T. Chao, M. Guzy","doi":"10.1109/ECTC.2006.1645663","DOIUrl":"https://doi.org/10.1109/ECTC.2006.1645663","url":null,"abstract":"This paper describes the technology development for packaging two identical CPU die on one package. Historically, processors involved packaging one die on a package, but with higher performance demands, multiple die products have become necessary. With existing single core die designs, packaging two die in one unit provides a novel way of producing a dual core CPU without designing new silicon. This paper starts with the evolution of dual core CPU from use of two die joined to each other to separate die placed next to each other to the final form of two die placed with a gap. The land grid array (LGA) package technology development was done within the boundary conditions of reuse of existing sockets and enabling solutions. It involved use of higher layer count substrates to allow routing of two die to pre-existing pin-out, modified IHS to accommodate two die in a limited space, and die side components for helping power delivery. The paper describes the details of the substrate technology, routing options and design rules to meet the dual die package requirements that include product performance, substrate manufacturing and assembly and test. The test vehicle definition and design of different structures are described that are new for the dual die scenario. Also limitations based upon compatibility requirements for test lead to creative implementations of those test vehicle structures. The IHS design modifications implemented to fit the two die and to maintain the over all package stack-up are described. Routing and power delivery methodologies in the dual die package architecture are described. Discussed also are how substrate design rules, & collaterals and design process changed and adjusted to the move from a single die to two. The paper then focuses on the multiple challenges faced by the assembly and reliability areas. Single chip package versus dual chip package mechanical stresses are compared. Assembly areas of chip attach, under-fill, and IHS attach are described. The process design rules for UF in dual die case are new compared with the single die case. The challenges of IHS attach and TIM process (including thicknesses) for the two separate die are addressed. Specific challenges encountered for multi-chip packages (MCP) include application of chip attach flux, removal of flux after chip attach as well as voids formed at the TIM to IHS interface. Finally, thermal performances of the dual die package are presented and compared with that of a single die package. The thermal definitions and measurement methods for the dual die package are shown with equivalents to single die case. The thermal benefits of a dual die package prove the advantages of a dual die package in terms of product performance with respect to power dissipation. The future directions of the dual die technology based on the new products on the roadmap are discussed along with some potential areas of focus in the next generation dual die packages","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133707303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}