B. Archambeault, S. Connor, D. de Araujo, A. Ruehli, C. Schuster
{"title":"Fullwave simulation and validation of a complex packaging structure","authors":"B. Archambeault, S. Connor, D. de Araujo, A. Ruehli, C. Schuster","doi":"10.1109/ECTC.2006.1645816","DOIUrl":null,"url":null,"abstract":"Most high data rate PCBs has many layers. Signals can change layers with many different configurations, and often have long stubs. All these options can have different effects on the signal, and need to be properly simulated. This paper describes the initial efforts to develop a strategy to properly analyze these complex structures by first modeling a simple via structure where a signal trace changes from one side of a reference plane to the other side of the same plane. No long via stubs are included initially. The complexity of the via structure is further increased by adding more metal layers, via stubs, and a return current via (at different distances from the signal via). Practical structures of increasing complexity are modeled such as those found in high-end servers and blade systems. The structures were simulated using a number of different simulation techniques: finite-difference time-domain (FDTD), partial element equivalent circuit (PEEC) as presented in A. E. Ruehli (1974), finite integration technique (FIT), and finite element method (FEM). It is widely accepted that if completely different simulation techniques are able to capture the proper physics of the problem and get the same results, then the simulation results are valid. Good agreement was obtained for all configurations","PeriodicalId":194969,"journal":{"name":"56th Electronic Components and Technology Conference 2006","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"56th Electronic Components and Technology Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2006.1645816","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Most high data rate PCBs has many layers. Signals can change layers with many different configurations, and often have long stubs. All these options can have different effects on the signal, and need to be properly simulated. This paper describes the initial efforts to develop a strategy to properly analyze these complex structures by first modeling a simple via structure where a signal trace changes from one side of a reference plane to the other side of the same plane. No long via stubs are included initially. The complexity of the via structure is further increased by adding more metal layers, via stubs, and a return current via (at different distances from the signal via). Practical structures of increasing complexity are modeled such as those found in high-end servers and blade systems. The structures were simulated using a number of different simulation techniques: finite-difference time-domain (FDTD), partial element equivalent circuit (PEEC) as presented in A. E. Ruehli (1974), finite integration technique (FIT), and finite element method (FEM). It is widely accepted that if completely different simulation techniques are able to capture the proper physics of the problem and get the same results, then the simulation results are valid. Good agreement was obtained for all configurations
大多数高数据速率pcb都有很多层。信号可以用许多不同的配置改变层,并且通常有很长的存根。所有这些选项都会对信号产生不同的影响,需要进行适当的模拟。本文描述了通过首先模拟一个简单的通孔结构来正确分析这些复杂结构的策略的初步努力,其中信号迹线从参考平面的一侧变化到同一平面的另一侧。最初不包括长via存根。通过增加更多的金属层、通孔存根和返回电流通孔(距离信号通孔不同的距离),进一步增加了通孔结构的复杂性。对日益复杂的实际结构进行建模,例如在高端服务器和刀片系统中发现的结构。采用多种不同的模拟技术对结构进行了模拟:时域有限差分(FDTD)、a . E. Ruehli(1974)提出的部分单元等效电路(PEEC)、有限积分技术(FIT)和有限元法(FEM)。人们普遍认为,如果完全不同的仿真技术能够捕获问题的适当物理性质并得到相同的结果,则仿真结果是有效的。对所有配置都获得了良好的一致性