2021 China Semiconductor Technology International Conference (CSTIC)最新文献

{"title":"Automatic Digital Modeling for Analog Blocks in Mixed-Signal Verification","authors":"Yang Leng, Zuochang Ye, Jian Xin, Zhikai Wang, Yan Wang","doi":"10.1109/CSTIC52283.2021.9461472","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461472","url":null,"abstract":"Analog circuits are indispensable in practical circuit design, even in digital circuit systems. Mixed-signal circuits often cost a lot of simulation time. In this paper, we propose an automatic digital modeling algorithm to speed up the mixed-signal simulation. The algorithm is based on dynamic mode decomposition (DMD), which converts the mixed-signal circuit into a pure digital circuit. Experiments shows >100X speed-up compared with mixed-signal simulation.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Gate-Cut Patterning Approaches Using Simulation and Defect Modelling","authors":"Sun Li Fei, Wang Qing Peng, Zhang Ji Hong, Chi Yu Shan","doi":"10.1109/CSTIC52283.2021.9461509","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461509","url":null,"abstract":"Gate patterning is a critical step during CMOS transistor fabrication. As devices scale down in dimension, the gate-cut process has become increasingly important due to its significant impact on device performance and chip yield. Different gate-cut approaches have been developed for varying node integration requirements. In this paper, several gate-cut approaches are simulated using SEMulator3D®, a process and defect modeling platform. The simulation revealed both advantages and disadvantages to various gate-cut patterning approaches and provided guidance on improved process flow selection. Dummy gate-cut process window checks, along with poly line end residue modelling, have also been completed during this study and highlighted areas for potential process improvements and defect reduction.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125998916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Picosecond Imaging Circuit Analysis of CMOS Circuits Using SIL Measurement","authors":"S. Lin, Frank Yong","doi":"10.1109/CSTIC52283.2021.9461429","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461429","url":null,"abstract":"As a process node is getting smaller, the types of failure mechanisms are increasing. New EFA technologies and methods are constantly development. One of the main changes EFA analyses is an enhancement of dynamic EFA in circuit failed in functional test. We propose a technique for advanced Electrical Failure Analysis (EFA) tool with a Picosecond Imaging Circuit Analysis (PICA) detector with enhanced sensitivity for discussing Time Resolved Emission (TRE). The key applications where the time-resolved imaging capability is very effective in reducing the debug time and improving the understanding the failure behaviors of VLSI chip for fault characteristics, especially the use of SIL(Solid Immersion Lens).","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Experimental Study on Void Growth and EM Performance Under Directional Current Reversal","authors":"Dingrui Zhang, Weihai Fan, Jizhou Li, Kelly Yang","doi":"10.1109/CSTIC52283.2021.9461514","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461514","url":null,"abstract":"In this paper, void growth and EM performance under directional current (DC) reversal have been studied by PLR EM. It's found that without DC reversal, void growth mode has one category (void increasing) and statistical void growth rate is positively linearly correlated with MTTF. With DC reversal, void growth mode has three categories (void increasing, void transition, and void refilling) whose proportions have not significant difference with each other (proportions are around 30%), MTTF of void refilling is about one time higher than forward, and overall EM performance with DC reversal shows better than that without DC reversal (MTTF increased by ~16%) for the same cumulative electric resistance shift.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133641057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Contact Misalignment on VT for Trench Power Mosfet","authors":"Perry Li, R. Qiu, H. Zhou, J. Liu, K. Yang, C. Xu, E. Wu, L. Du, K. Lin, J. Feng, M. Chi","doi":"10.1109/CSTIC52283.2021.9461420","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461420","url":null,"abstract":"Power ICs and devices, as key components for high performance systems with Artificial-Intelligence and Internet-of- Things (AI/loT), need to have superior quality and reliability with low Ron and good breakdown voltage. This paper briefly describes how the internal Vt's are impacted by the spacing from contact edge to the vertical channel. The trans-conductance of Id vs Vg is sensitive to detect the internal Vt's. The power MOS and IGBT with multiple Vt's can be formed by designing the contact layout with intentional varying the spacing to the vertical channel for digital info storage in new applications.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115605406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of Different Gate Stress Conditions on Hot Carrier Injection in High Voltage N-Channel CMOS","authors":"Lei Li, Sarah Zhou, Kelly Yang","doi":"10.1109/CSTIC52283.2021.9461476","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461476","url":null,"abstract":"Generally, the gate voltage (V<inf>g</inf>) stress condition for the worst HCI effect corresponds to the maximum I<inf>sub</inf> with drain voltage (V<inf>d</inf>) being fixed at 1.1 times operation voltage (1.1xV<inf>dop</inf>). However, in our HV n-channel CMOS device, the HCI largest degradation occurred at 1.1 times <tex>$V_{g}$</tex> operation voltage (1.1xV<inf>gop</inf>) instead of the maximum substrate current (I<inf>bmax</inf>). In this paper, we used charge pumping (CP) technique to detect the interface traps and oxide traps during HCI degradation. It was found that interface traps were responsible for the degradation at the <tex>$V_{g}$</tex> corresponding to I<inf>bmax</inf> near the drain side, while interface traps and negative oxide traps induced by larger vertical electric field were together predominant for the degradation at V<inf>g</inf> = 1.1 x V<inf>gop</inf>. The dependence of HCI on <tex>$V_{g}$</tex> was further investigated through Technology Computer Aided Design (TCAD) simulation and consistent conclusion was found.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124204994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimizing the Energy Efficiency of Switched-Capacitor Converters in Multiprocessor System-on-Chips with a Preset DVFS Policy","authors":"Linfeng Zheng, Pingqiang Zhou","doi":"10.1109/CSTIC52283.2021.9461260","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461260","url":null,"abstract":"Some multiprocessor system-on-chips (MPSoCs) provide designers with workload information in early chip planning stage to optimize the chip's performance. In our work, we focus on the energy efficiency of switched-capacitor converters (SCCs) in MPSoCs to efficiently support dynamic voltage and frequency scaling (DVFS). Two things motivate us to propose our design flow in MPSoCs, i.e. 1) Recent work allocates Metal-Insulator-Metal (MIM) capacitance and selects a converter ratio for each SCC to reach a higher energy efficiency. However, it brings the high overhead of its hardware implementation for various voltage and current demands. 2) DVFS policy has an unbalance distribution of its scaling decisions, which further results in an unbalance distribution of the voltage and current demands. Based on these, in our design flow, the hotspot recognition and the look-up table techniques help us to overcome the shortcomings of the recent work and harvest the benefits of the recent work. The experiment explores the different hotspot capacities' effects on energy efficiency and overhead.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114442240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frontiers in Low-Frequency Noise Research in Advanced Semiconductor Devices","authors":"E. Simoen, A. Veloso, B. O’Sullivan, K. Takakura, C. Claeys","doi":"10.1109/CSTIC52283.2021.9461526","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461526","url":null,"abstract":"The paper gives an overview of low-frequency noise studies in advanced semiconductor devices, targeting at different applications. As will be shown, the choice of substrate (bulk Si versus SOI) determines to a large extent the noise behavior of Gate-AII-Around (GAA) Vertical Nanowire (VNW) FETs. While no shot noise above 100 Hz is found for devices on SOI, the dominant flicker noise is of number fluctuations origin, in contrast to mobility fluctuations for the devices with a back-silicon source contact on bulk. It will be shown that the 1/f noise of Si-doped orthorhombic Hf02 is a factor of three lower than for paraelectric Hf02. Finally, the noise performance for GaN-on-Si based HEMTs, MOSHEMTs and MOSFETs will be compared and briefly discussed.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114843573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of planarizing spin-on carbon material for high-temperature processes","authors":"R. Huang, X. Zhong, J. Koza, G. Xu, Boyu Zhang, Sean Simmons","doi":"10.1109/CSTIC52283.2021.9461452","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461452","url":null,"abstract":"For the last several advanced semiconductor nodes, as the industry moves towards 7- and 5-nm processes, the requirements for patterning and image transfer have increased dramatically. Multilayer material stacks are needed to pattern complex high-resolution structures. For carbon films, one key point is the tradeoff between planarization and high-temperature stability requirements used in patterning and post-patterning process integration. On one side, the need for thermally stable carbon materials is steadily increasing, for better pattern transfer fidelity (less line wiggling), chemical vapor deposition (CVD) compatibility where a plasma-enhanced CVD (PECVD) inorganic hardmask is deposited on top, and for the use as mandrels for pattern multiplication. On the other hand, due to the increased complexity of chip designs, gap filling and planarization of the underlying topography is also strongly desired. In addition, wet chemical resistance and the capability to be polished by chemical mechanical planarization (CMP) processes are often necessary. Design of a spin-on carbon (SOC) film to meet all the desired, but sometimes conflicting, properties using organic polymers with good solubility in fab-approved solvent systems requires innovative chemical design and rigorous experiment and tuning processes. Brewer Science's advanced material development is bringing forth low-shrinkage, high-temperature-stable SOCs with spin-bowl/drain compatibility for advanced node manufacturing and integration. The materials presented in this paper are stable up to 500-550°C with no weight loss, soluble in solvents commonly used in semiconductor industry, can fill <10 nm narrow gaps, and have excellent planarization properties over a long distance. The coated film has very low thickness shrinkage during the bake conditions on the track and is stable through the subsequent high temperature PECVD process. The resulting dense carbon film provides extremely good planarization both locally and globally across the wafer. It demonstrated great chemical resistance to SC 1 conditions and can be CMP polished using commercially available slurries, if needed. During etch transfer, it showed very little after-develop inspection (ADI) and after-etch inspection (AEI) bias and maintained excellent line-width resolution through various critical dimensions. Moreover, this material's good solubility allows it to be formulated with high solid content for >2 µm thickness, which has showed early promising results in filling some very-high-aspect-ratio gaps in certain memory applications.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123709951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on Low Power Back-Side Deep Trench Isolation Etching on Stack-BSI CMOS Image Sensor","authors":"Zhu Yin, Jianjun Li, Xinruo Su, Dejing Ma, Hanming Wu, Xing Zhang","doi":"10.1109/CSTIC52283.2021.9461581","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461581","url":null,"abstract":"The leakage of pixel is a significant index to characterize quality of CMOS image sensor (CIS), which is classified into white pixel (WP) and dark current (DC) in the yield test. It is widely observed by researches that WP and DC are induced by metal contamination or plasma damage. And many solutions are attempted in order to reduce WP and DC. One of a popular method is, for the back-side illuminated (BSI) product, deep trench isolation (DTI) with high-K film by holes accumulation layer formation. However, this passivation film could not be strong enough for pixel protection if the deep trench etching is produced by high power process or unreasonable integration. So deep study is excused by this paper on both lower down the plasma damage and remove plasma damaged region. And the benefit result of experiment is shown finally.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"253 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125787155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}