Effects of Different Gate Stress Conditions on Hot Carrier Injection in High Voltage N-Channel CMOS

Abstract

Generally, the gate voltage (Vg) stress condition for the worst HCI effect corresponds to the maximum Isub with drain voltage (Vd) being fixed at 1.1 times operation voltage (1.1xVdop). However, in our HV n-channel CMOS device, the HCI largest degradation occurred at 1.1 times $V_{g}$ operation voltage (1.1xVgop) instead of the maximum substrate current (Ibmax). In this paper, we used charge pumping (CP) technique to detect the interface traps and oxide traps during HCI degradation. It was found that interface traps were responsible for the degradation at the $V_{g}$ corresponding to Ibmax near the drain side, while interface traps and negative oxide traps induced by larger vertical electric field were together predominant for the degradation at Vg = 1.1 x Vgop. The dependence of HCI on $V_{g}$ was further investigated through Technology Computer Aided Design (TCAD) simulation and consistent conclusion was found.