Study on Low Power Back-Side Deep Trench Isolation Etching on Stack-BSI CMOS Image Sensor

Abstract

The leakage of pixel is a significant index to characterize quality of CMOS image sensor (CIS), which is classified into white pixel (WP) and dark current (DC) in the yield test. It is widely observed by researches that WP and DC are induced by metal contamination or plasma damage. And many solutions are attempted in order to reduce WP and DC. One of a popular method is, for the back-side illuminated (BSI) product, deep trench isolation (DTI) with high-K film by holes accumulation layer formation. However, this passivation film could not be strong enough for pixel protection if the deep trench etching is produced by high power process or unreasonable integration. So deep study is excused by this paper on both lower down the plasma damage and remove plasma damaged region. And the benefit result of experiment is shown finally.