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2021 China Semiconductor Technology International Conference (CSTIC)最新文献

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Complex Protocol Construct System on ATE Platform ATE平台上的复杂协议构建系统
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461465
Xinze Song, Man Cao
{"title":"Complex Protocol Construct System on ATE Platform","authors":"Xinze Song, Man Cao","doi":"10.1109/CSTIC52283.2021.9461465","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461465","url":null,"abstract":"SOCs and SIPs require internal register programming to configurate applicable operating mode before and RF, analog, or DC test. The traditional method is that the DFT (Design for Test) engineer provides vector configuration (WGL file), and these will be transformed into ATE (Auto Test Equipment) patterns. We call this process ATE pattern iteration. Meanwhile, there are several problems when iterating. It costs long time and has poor interactivity. Besides this situation, DFT engineers usually design multiple interface protocols to meet different chip application scenarios. For these situations, we design a solution which can be easy to configure or re-program chip registers to reduce the ATE pattern iteration times, be easy to use different protocol to avoid extra code development.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121346794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Etching Morphology of Silver Study by Inductively Coupled Ar-Based Plasmas 电感耦合ar基等离子体刻蚀银的形貌研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461479
Qingqing Lian, Ruiping Zhu, Wang Jing, Hailong Liu, Zhongwei Jiang
{"title":"The Etching Morphology of Silver Study by Inductively Coupled Ar-Based Plasmas","authors":"Qingqing Lian, Ruiping Zhu, Wang Jing, Hailong Liu, Zhongwei Jiang","doi":"10.1109/CSTIC52283.2021.9461479","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461479","url":null,"abstract":"The main difficulty of silver etching is that non-volatile by-products are easily generated during the etching process, these by-products cover the surface of the material or mask, which affects the etching and difficult to remove. In this paper, we have studied the influence of different gas on silver etching, and compared the morphology before and after wet stripping. In the experiment, under the condition of a larger flow rate of Ar, larger bias voltage and a small amount of CH4 were added, and the etching results were better.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"69 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123245187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep and Vertical Polyimide Etching 深度和垂直聚酰亚胺蚀刻
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461562
Yuwei Kong, Yuanwei Lin, Zihan Dong
{"title":"Deep and Vertical Polyimide Etching","authors":"Yuwei Kong, Yuanwei Lin, Zihan Dong","doi":"10.1109/CSTIC52283.2021.9461562","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461562","url":null,"abstract":"Polyimide (PI) has been used widely in electronic device manufacture process, such as micro-electro-mechanical systems (MEMS) device and advanced packaging. Due to the limitation of the manufacture process, in general, patterned PI with depth of less than 10 µm is usually adopted in these applications. In this work, a cyclic deposition/etch method is demonstrated, and the patterned PI with depth of more than 30 µm and nearly vertical profile is obtained. Furthermore, the carbonization of PI is avoided by controlling the forward source/bias power and temperature during the etch process. The etch method and structure may be useful in the research and development of some new devices.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123584806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Study on Retest Reduction by Minimizing Probe Card Contact Resistance at Wafer Test 减少晶圆测试中探针卡接触电阻的复测研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461487
Hua Li, Deguang Zheng
{"title":"Study on Retest Reduction by Minimizing Probe Card Contact Resistance at Wafer Test","authors":"Hua Li, Deguang Zheng","doi":"10.1109/CSTIC52283.2021.9461487","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461487","url":null,"abstract":"To study the mechanism how to minimize the probe card contact resistance as to take least retest operation during wafer test. Calculate the retest rate with variant approaches to reduce the contact resistance between probe card needles and silicon wafer. A design of experiment (DOE) is used to find the most effective cleaning parameters and to spot the threshold of cleaning parameters set which is a balance for a good needle cleaning performance and reasonable probe card life. Deliver a formular to calculate retest rate with given cleaning parameters and locate the optimization values to achieve the lowest retest rate.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123696724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Combination Design of 3D Depth Imaging and 2D Intensity Imaging SPAD Device Circuit 三维深度成像与二维强度成像SPAD器件电路的组合设计
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461525
Xiangshun Kong, Guisheng Zhao, Xiong Yang, Hao Chen, Feng Yan, Cheng Mao
{"title":"A Combination Design of 3D Depth Imaging and 2D Intensity Imaging SPAD Device Circuit","authors":"Xiangshun Kong, Guisheng Zhao, Xiong Yang, Hao Chen, Feng Yan, Cheng Mao","doi":"10.1109/CSTIC52283.2021.9461525","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461525","url":null,"abstract":"In this paper, a SP AD device array and circuit for combination of 3D depth imaging and 2D intensity imaging are proposed. Switching between 2D intensity imaging and 3D distance detection can be achieved by mode selection. The on chip TDC has 100 ps time precision in 3D mode and shares a 12-bit counter with the 2D intensity mode. The array size is 1 × 128 and a two-dimensional image can be obtained by rotating or pushing camera system. The chip can be used in lidar, depth imaging, topographic mapping and other fields.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliability Challenges and Inline Metrology - An Effective Approach to Implementation in Advanced Devices 可靠性挑战和在线计量——在先进设备中实现的有效方法
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461473
D. Fishman, Sang-Hyun Han
{"title":"Reliability Challenges and Inline Metrology - An Effective Approach to Implementation in Advanced Devices","authors":"D. Fishman, Sang-Hyun Han","doi":"10.1109/CSTIC52283.2021.9461473","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461473","url":null,"abstract":"As semiconductor devices scale down in size, the sensitivity of reliability to process variation increases. This increase is due to the high-reliability requirements for advanced system applications, the narrowing process margins, and the high sensitivity of devices to composition. At the process level, specific materials or process chambers can degrade the devices' reliability, induced by additional charge traps in the adjacent cells and poor data retention due to contamination by killer elements and complex structures, although they may be required from a process integration perspective. It is difficult to effectively detect killer elements during the process, which can create or accelerate reliability failure. Several killer elements cause reliability degradation: F (fluorine), CI (Chlorine), local strains in the SiGe layers, and plasma-induced traps at the gate oxide interfaces. We find that an effective approach to prevent reliability failure is to monitor potential killer elements in the process, maintain them under threshold levels and screen out heavily contaminated wafers before wafer fab-out. This paper addresses the relationship between specific killer elements and reliability and reviews the enablers of inline metrology that can prevent reliability failure by early detection and monitoring of variation of killer elements in fabs.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115335787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ashing Process on Warpage Wafer with Low Damage 低损伤翘曲片的灰化工艺
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461448
Zihan Dong, Yuanwei Lin, Yuwei Kong
{"title":"Ashing Process on Warpage Wafer with Low Damage","authors":"Zihan Dong, Yuanwei Lin, Yuwei Kong","doi":"10.1109/CSTIC52283.2021.9461448","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461448","url":null,"abstract":"To improve the surface quality of polyimide (PI) or photoresist (PR) ashing/striping on warpage wafer, the issues of arcing, peeling and damage should be overcome. In this work, we demonstrate a time-multiplexed alternating ashing (TMAA) process for 12-inch warpage wafer. The TMAA process can reduce the risk of arcing and peeling with higher uniformity. Therefore, the TMAA process is a low cost and highly efficient method for the surface treatment in advanced packaging.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116105015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The photoresist developing ability study at different contact angle and mask transmission rate 研究了不同接触角和掩膜透射率下光刻胶的显影能力
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461568
C. Lijun, Zheng Haichang, W. Xiaolong, Qin Lipeng, C. Jiawen, Yin Pengteng
{"title":"The photoresist developing ability study at different contact angle and mask transmission rate","authors":"C. Lijun, Zheng Haichang, W. Xiaolong, Qin Lipeng, C. Jiawen, Yin Pengteng","doi":"10.1109/CSTIC52283.2021.9461568","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461568","url":null,"abstract":"The PFOA surfactant (chemical structure: (polymer backbone)-C8F17) using in photoresist is forbade own to every country need protect environment, so the PFOA surfactant is replaced by non PFOA type (chemical structure: (polymer)-(CF2)n2-CF3, n2<4*). Along with the variation, some photoresist contact angle change from 78 degree to 72 degree. The relation between PR contact angle and developing ability is studied in our paper. At the higher contact angle of PFOA photoresist version, weak developing process is not suitable. The results using weak developing recipe show that the lower transmission rate of mask, the worse abnormal CD at wafer edge (abnormal CD: 412nm, normal CD: 344 nm), and the layer with high transmission rate does not have same issue. On the opposite, stronger developing recipe causes high transmission rate layer wafer edge pattern peeling at the lower contact angle of non PFOA photoresist version. In addition, the develop process settings suitable for different contact angle are also studied, which include developing pre wet time optimize.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116236818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ApproxDNNFlow: An Evaluation and Exploration Framework for DNNs with Approximate Multipliers ApproxDNNFlow:一个带有近似乘数的深度神经网络的评估和探索框架
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461574
Jide Zhang, Su Zheng, Lingli Wang
{"title":"ApproxDNNFlow: An Evaluation and Exploration Framework for DNNs with Approximate Multipliers","authors":"Jide Zhang, Su Zheng, Lingli Wang","doi":"10.1109/CSTIC52283.2021.9461574","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461574","url":null,"abstract":"Widely used deep neural networks (DNNs) are proved error-tolerant, therefore accurate multipliers in DNNs can be replaced by approximate multipliers to reduce the power consumption. We set up a framework for training and evaluating DNNs based on approximate multipliers. Noisy training is proposed to adjust the parameters to tolerate the error caused by the approximate multipliers. Moreover, the framework can evaluate DNN accuracies with approximate multipliers. In the experiment, four approximate multipliers are evaluated. Based on the DNN inference results on MNIST and CIFAR10 by LeNet, the selected approximate multiplier can reach 99.17% and 65.76% accuracies respectively (the original accuracies are 99.27% and 74.88%) with significant reduction of the power consumption and area. In addition, the inference accuracies can be improved up to 99.21% and 69.5% by the proposed noise training methods. The proposed framework can contribute to the design of effective approximate computing for DNNs in the future.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122857039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ATE Test Solution for High Resolution and High Voltage DAC 高分辨率和高压DAC的ATE测试解决方案
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461575
Tianyu Zhang, Jian Wang, Juyang Sun
{"title":"ATE Test Solution for High Resolution and High Voltage DAC","authors":"Tianyu Zhang, Jian Wang, Juyang Sun","doi":"10.1109/CSTIC52283.2021.9461575","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461575","url":null,"abstract":"High resolution DAC production test is always a difficult problem in mixed signal testing. However, high resolution and high voltage DAC testing is more difficult. Many factors need to be considered in the test of high resolution and high voltage DAC, including the spec of the measurement instrument, the feasibility of the test plan, the actual production efficiency. This paper proposes an ATE test solution for a 32-channel, 14Bit DAC with full-scale output voltage 65V. The hardware solution is based on AVI64 card of 93K platform, which can achieve the measurement resolution of 0.2mV when the measurement range is -40V-80V. The digitizer feature of AVI64 enables direct sampling of chip output waves at sampling rates up to 1MHz. Meanwhile, 4 site parallel test is realized combined with relay switch on load board. The software solution is to design a framework based on the idea of high cohesion and low coupling, which include register configuration based on SPI protocol, IP test realization and common function. Finally, the mass production test of this high resolution and high voltage DAC was realized based on this solution, the result shows that INL is 4 LSB and DNL is 2.5 LSB, which is well correlated with EVB result in lab.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128607563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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