Complex Protocol Construct System on ATE Platform

Abstract

SOCs and SIPs require internal register programming to configurate applicable operating mode before and RF, analog, or DC test. The traditional method is that the DFT (Design for Test) engineer provides vector configuration (WGL file), and these will be transformed into ATE (Auto Test Equipment) patterns. We call this process ATE pattern iteration. Meanwhile, there are several problems when iterating. It costs long time and has poor interactivity. Besides this situation, DFT engineers usually design multiple interface protocols to meet different chip application scenarios. For these situations, we design a solution which can be easy to configure or re-program chip registers to reduce the ATE pattern iteration times, be easy to use different protocol to avoid extra code development.