2021 China Semiconductor Technology International Conference (CSTIC)最新文献_第10页

Machine Learning Assisted In-Situ Sensing and Detection on System of PECVD Depositing Hydrogenated Silicon Films 机器学习辅助PECVD沉积氢化硅膜系统的原位传感与检测

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461536

Yu-Pu Yang, Hsiao-Han Lo, Wei-Lun Chen, Song-Ho Wang, T. Lu, Hsueh-Er Chang, Peter j. Wang, Walter Lai, Y. Fuh, Tomi T. T. Li

引用次数: 0

Wi-Fi 6E Test Challenges on ATE Wi-Fi 6E测试对ATE的挑战

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461416

Ping Wang, Mason Zhang, Zhiqiang Bai, Haixia Guo, Eng-Keong Tan

引用次数: 0

Super Junction by Implant through Trench Contact for Low-Voltage Power MOSFET and IGBT 低压功率MOSFET和IGBT的沟槽接触超级结

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461552

Janifer Liu, P. Li, R. Qiu, H. Zhou, K. Yang, C. Xu, E. Wu, L. Du, K. Lin, J. Feng, M. Chi

引用次数: 0

Valid Test Pattern Identification for VLSI Adaptive Test VLSI自适应测试的有效测试模式识别

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461537

Tai Song, Tianming Ni, Zhengfeng Huang, Ji Wan

引用次数: 5

A Novel Toffoli Gate Design Using Quantum-dot Cellular Automata 基于量子点元胞自动机的新型Toffoli门设计

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461426

Huiming Tian, Zhufei Chu

引用次数: 1

Optical Proximity Correction, Methodology and Limitations 光学接近校正，方法和限制

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461507

Y. Hou, Qiang Wu

{"title":"Optical Proximity Correction, Methodology and Limitations","authors":"Y. Hou, Qiang Wu","doi":"10.1109/CSTIC52283.2021.9461507","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461507","url":null,"abstract":"Since the early 2000's, model based Optical Proximity Correction (MB-OPC) has been used by the semiconductor industry to improve the linewidth uniformity and pattern fidelity in photolithography. Designed to be improved from its predecessor, the rule based OPC (RB-OPC), which relies on a table of biases to correct linewidth variation due to Optical Proximity Effect (OPE), it uses aerial image to calculate pattern edge deviation from the design. The flow of the MB-OPC includes the model data collection, model setup and calibration, recipe setup, OPC correction and post-OPC verify check. Since the OPC process also include the addition of assist patterns, such as serif, Sub-Resolution Assist Features (SRAF), and hammer heads, etc., the OPC process can also help improve lithography process window. Albeit above advantages, OPC can have modeling errors which may cause pattern failures and re-toolings. The modeling error is understood to basically originate from non-perfect physical modeling of the lithography process, which implies the need for better modeling. Better modeling includes better photoresist characterization and modeling, better Mask 3D (M3D) scattering effect modeling, and better developing process characterization, etc. It is also related to the quality of patterning process setup, such as the optimization of the substrate film stack, mask bias, and the photoresist process, and Reactive Ion Etch (RIE) bias, etc. Once the OPC model is optimally setup, the correction recipe setup will be less challenging and can focus on difficult areas, such as few line structures, complicated 2D features, etc. In this paper, we propose a methodology in model calibration and recipe setup and will provide recommendation on the effective use of optical proximity correction.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"51 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114093847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Novel Lightweight PUFs Using Interconnect Line Mismatch for Hardware Security 一种利用互连线不匹配实现硬件安全的新型轻量级puf

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461415

Ye Lin, Yuejun Zhang, Jia Chen, Jinliang Han

{"title":"A Novel Lightweight PUFs Using Interconnect Line Mismatch for Hardware Security","authors":"Ye Lin, Yuejun Zhang, Jia Chen, Jinliang Han","doi":"10.1109/CSTIC52283.2021.9461415","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461415","url":null,"abstract":"The emerging physical unclonable functions (PUFs) in the IC supply chain pose not only a challenge to security threats, but also a serious concern about hardware efficiency. Traditional PUF relies on the mismatch of the device, and it may occupy lager area of the chip. In this paper, the physical unclonable function based on interconnect line mismatch is proposed with lightweight property. Due to the inevitable random difference in the process of the interconnect, the delay of the two lines will be different, to produce the random data of the PUF circuits. Then, PUF array is designed with control circuit, PUF cell circuit, and output circuit. Under the TSMC 65 nm CMOS technology, the proposed PUF can provide the physical random entropy source. Using Cadence simulation EDA tools, the experiments are performed to evaluate the performance of PUF circuits. And it operates at 1.2 V, ensures randomness and uniqueness with 48.6% hamming distance. Compared with other state-of-the-arts, the hardware cost reduces more than 15%. The experiment results show that interconnect line PUF provides better lightweight and randomness.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121490110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Peeling Defect Studying with N2/H2 Plasma during Carbon-based Recess Etch 碳基凹槽刻蚀过程中N2/H2等离子体剥落缺陷的研究

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461561

Jinrong Wu, Junwen Huang, Taojun Zhuang, Weijun Luo, Victor Fang, C. Lansford, Yun Chen, Martin Liu, Scott Shao

引用次数: 0

A Novel Wafer-Map Similarity Search System with High Speed and Accuracy 一种高速、高精度的晶圆图相似度搜索系统

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461570

Chang Xu, Qinfeng Shi, Ping-Fen Shi

引用次数: 0

High-K Bubble Defect Researches in Stack-BSI Process Product 堆叠- bsi工艺产品高k泡缺陷研究

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461252

Zhu Yin, Jianjun Li, Xiaoping Li, Na Zhu, Lifeng Liu, Hanming Wu, Dejing Ma, Xing Zhang

引用次数: 1