Valid Test Pattern Identification for VLSI Adaptive Test

Abstract

During manufacturing test, more and more test patterns are added to test set to achieve acceptable defect levels, which seriously affect test cost. This paper proposes a kind of eliminate redundancy pattern method, so that this MRMR (Max-Relevance Min-Redundancy) algorithm which can provide test cost reduction without increasing the defect level obviously. Experiment results demonstrate that the valid test patterns have higher test quality, which can reduce the test time and test cost of the faulty circuit. The algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process.