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Negative-Tone Imaging (NTI) for Advanced Lithography With EUV Exposure to Improve ‘Chemical Stochastic’ EUV曝光先进光刻技术的负色调成像(NTI)改善“化学随机”
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461523
Toru Fujimori
{"title":"Negative-Tone Imaging (NTI) for Advanced Lithography With EUV Exposure to Improve ‘Chemical Stochastic’","authors":"Toru Fujimori","doi":"10.1109/CSTIC52283.2021.9461523","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461523","url":null,"abstract":"Extreme ultraviolet (EUV) lithography is almost ready for realize 7nm generation manufacturing and beyond. A key factor for the realization of EUV lithography is the choice of EUV resist materials that are capable of resolving below 15nm half pitch with high sensitivity. However, the performance of EUV resist materials is still not enough for the true HVM requirements. One critical issue is ‘Chemical stochastic’, which will be become ‘defectivity’. We report herein to improve of ‘Chemical Stochastic’ by using negative-tone imaging (NTI) process with EUV exposure. Also, the other options will be introduced.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effective Radiation Damage to Floating Gate of Flash Memory 闪存浮栅的有效辐射损伤研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461408
C.-Z. Chen, D. Y. Hu, Hanming Wu
{"title":"Effective Radiation Damage to Floating Gate of Flash Memory","authors":"C.-Z. Chen, D. Y. Hu, Hanming Wu","doi":"10.1109/CSTIC52283.2021.9461408","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461408","url":null,"abstract":"Non-volatile memory (NVM) devices, based on floating gate (FG) technology, including EEPROM, NAND and OR Flash memories, are increasingly used today in both consumer products and high-end applications. Quality of 3D NAND Flash in solid-state drive (SSD) storage used in data center, automotive and space science is critical. While NOR Flash used in TWS earbuds for smartphones and IoT/5G products offers a quality of live option. To ensure reliability of the high-end products, e.g. for space application where ionizing radiation can produce potential damage to FGs, single event effects (SEEs) and total ionizing dose (TID) are typical assessments to evaluate product quality of Flash memory, subject to ionizing radiation particles of different energy and hence linear energy transfer (LET) in interactions with CMOS materials, Si and SiO2. Reported studies of SEE and TID using energy; stopping power (SP or S) or LET on various Flash memories are numerous. However, the quantitative results at various energy, S or LET can be misleading, as neither energy nor LET is an ideal quality factor in interpreting radiation hazards. Based on previous analysis of various radiation particles in CMOS silicon gate, the current study is extended to using the characteristics of range (R) of particle trajectory and specific ionization (Is) to analyze mean free path (Δ, distance between two ionization events) of electron, proton and several heavy ions in FG of Flash memory and the impact of electric charges generated by ionizing radiations. In the past decades the silicon process (of the gate length) has progressed from 100 nm down to 10 nm, our work further aims to explore effective radiation damage of SEE and TID by different types of particles, with respect to gate sizes of NVM cells.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125261914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Study of TSV-Induced and Strained Silicon-Enhanced Stress in 3D-IC 3D-IC中tsv诱导和应变硅增强应力的研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461503
Jindong Zhou, Yuyang Chen, Y. Jing, Pingqiang Zhou
{"title":"The Study of TSV-Induced and Strained Silicon-Enhanced Stress in 3D-IC","authors":"Jindong Zhou, Yuyang Chen, Y. Jing, Pingqiang Zhou","doi":"10.1109/CSTIC52283.2021.9461503","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461503","url":null,"abstract":"In this work, we discuss the influences of strained silicon technology on transistors in the context of TSV thermal stress. An accurate thermal stress distribution around a single TSV is firstly obtained by finite element analysis. Then we simulate the transistors using strained silicon technology and apply the TSV stress to the structure to study their magnitudes and mutual influences. It is demonstrated that the stress distribution combination of these two stress sources of planar transistors can be viewed as the superposition of the separate results. Finally, based on the updated stress distribution, the mobility variations of transistors around the TSV are studied.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124702256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Convolutional Neural Network (CNN) Based Automated Defect Classification (ADC) with Imbalanced Data 基于卷积神经网络(CNN)的不平衡数据自动缺陷分类(ADC)
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461464
Hairong Lei, Cho-Huak Teh, Zhe Wang, Gino Fu, Lingling Pu, Wei Fang
{"title":"Convolutional Neural Network (CNN) Based Automated Defect Classification (ADC) with Imbalanced Data","authors":"Hairong Lei, Cho-Huak Teh, Zhe Wang, Gino Fu, Lingling Pu, Wei Fang","doi":"10.1109/CSTIC52283.2021.9461464","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461464","url":null,"abstract":"Recently, deep learning (DL) convolutional neural network (CNN) has been employed for automated defect classification (ADC), with its diverse modeling approaches and network configurations, aiming to provide the best performance classifiers for wafer defect inspection. However, in semiconductor wafer inspection, critical killer defects data samples are usually very few although it is critical to classify these defects correctly in early stage of the wafer inspection process. Without specifically handling the imbalanced data problem, a classifier induced from the imbalanced data set is more likely to be biased towards the majority class and results in very poor classification result on the minority class (critical killer defects). This paper proposes a CNN for wafer ADC while addressing class imbalance issue via generative adversarial network (GAN) generated images. The experimental imbalanced dataset, consisting of scanning electron microscopy (SEM) images, is collected with ASML-HMI inspection tools.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116386671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Effect of FA/O II Surfactant as a Complex Non-Ionic Surfactant on Copper CMP FA/ oii表面活性剂作为络合非离子表面活性剂对铜CMP的影响
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461470
Yinchan Zhang, X. Niu, Jiakai Zhou, Chenghui Yang, Ziyang Hou, Yebo Zhu
{"title":"Effect of FA/O II Surfactant as a Complex Non-Ionic Surfactant on Copper CMP","authors":"Yinchan Zhang, X. Niu, Jiakai Zhou, Chenghui Yang, Ziyang Hou, Yebo Zhu","doi":"10.1109/CSTIC52283.2021.9461470","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461470","url":null,"abstract":"The surfactant in the slurry can optimize the surface uniformity and surface topography of the wafer to realize the global planarization, so the effect of FA/O II surfactant as a complex non-ionic surfactant in a glycine-based weakly alkaline slurry during the copper chemical mechanical planarization (CMP) process was discussed. The experimental results verified FA/O II surfactant can achieve a higher material removal rate (MRR) and lower within-wafer non-uniformity (WIWNU) than fatty alcohol polyoxyethylene ether (JFCE). A series of measurements confirmed that FA/O II surfactant can reduce surface tension and improve the uniformity and the topography of polished surfaces. The action mechanism of FA/O II surfactant was also analyzed.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121556474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effects of Surfactants on Cu-Co Galvanic Corrosion in Post-CMP Cleaning 表面活性剂对cmp清洗后Cu-Co电偶腐蚀的影响
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461255
Yazhen Wang, B. Tan, Shihao Zhang, Mengrui Liu, Xiaoqin Sun
{"title":"Effects of Surfactants on Cu-Co Galvanic Corrosion in Post-CMP Cleaning","authors":"Yazhen Wang, B. Tan, Shihao Zhang, Mengrui Liu, Xiaoqin Sun","doi":"10.1109/CSTIC52283.2021.9461255","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461255","url":null,"abstract":"In the post CMP cleaning of copper interconnects, the residual particles on copper surface should be removed and the interface corrosion defects between copper and barrier layer cobalt should be minimized. Surfactants are commonly used in post CMP cleaning. In this paper, the effects of different concentrations of two surfactants, linear alkylbenzenesulfonic acid(LABSA) and isooctanol polyoxyethylene ether(JFCE), on the corrosion potential difference of Cu and Co were studied by electrochemical method. The results show that both surfactants can significantly reduce the corrosion potential difference of Cu and Co, and the effect of LABSA is better, also the particles on the surface of copper have obvious removal effect.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advantages of Picosecond Ultrasonic Technology for Advanced RF Metrology 皮秒超声技术在先进射频计量中的优势
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461541
J. Dai, Johnny Mu, C. Kim, P. Mukundhan
{"title":"Advantages of Picosecond Ultrasonic Technology for Advanced RF Metrology","authors":"J. Dai, Johnny Mu, C. Kim, P. Mukundhan","doi":"10.1109/CSTIC52283.2021.9461541","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461541","url":null,"abstract":"Picosecond Ultrasonics (PULSE™Technology) has been widely adopted as the tool-of-record for metal film thickness metrology in semiconductor fabs around the world. It provides unique advantages, such as being a rapid, non-contact, nondestructive technology, and has capabilities for simultaneous multiple layer measurement. In this paper, we describe the unique advantages of Picosecond Ultrasonics for advanced radio frequency (RF) applications. RF filter process control requires stringent metrology due to tight process tolerances. The first principles-based PULSE technology does not require external calibration standards and provides robust measurement capability for multi-layer thickness measurements. For advanced RF applications, the capability of PULSE technology to measure both velocity and thickness simultaneously for transparent and semi-transparent films offers a lot of potential for not only monitoring processes but offers insight into the device performance. The PULSE technique can also simultaneously measure full stack for multilayer metal stack measurements with excellent repeatability and long-term stability which makes process control more efficient and reliable. Fast throughput makes it possible for high sampling rate for RF applications which is the key for device level process control and yield improvement.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Gate Length Dependence of Single Event Upset in 14Nm Bulk and SOI Finfetc Sram Cells 14Nm块体和SOI finfets Sram细胞中单事件扰流的栅极长度依赖性
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461413
Jingyi Liu, X. An, Gensong Li, Zhexuan Ren, Kunlei Gu, Ru Huang
{"title":"The Gate Length Dependence of Single Event Upset in 14Nm Bulk and SOI Finfetc Sram Cells","authors":"Jingyi Liu, X. An, Gensong Li, Zhexuan Ren, Kunlei Gu, Ru Huang","doi":"10.1109/CSTIC52283.2021.9461413","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461413","url":null,"abstract":"In this paper, the impact of gate length on Single Event Upset (SEU) characteristics of 14 nm bulk and SOI FinFET 6T SRAM is investigated and compared by mixed-mode 3D TCAD simulation. Simulation results show that for both bulk and SOI FinFET SRAM cells, the threshold linear energy transfer (LETth) decreases with decreasing the gate length. The LETth of SOI FinFET SRAM is larger but decreases more rapidly compared with bulk FinFET SRAM. Besides, the critical charges (Qe-«) and collected charges (Qeen) are analyzed to explain the gate length dependence of LETth in FinFET SRAM cells. The results imply that as the gate length shrinks, the SEU susceptibility of bulk and SOI FinFET SRAM becomes more severe, especially for SOI FinFET SRAM.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126373886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of the optical properties of a-Si:H films deposited by PECVD using various experimental techniques 利用各种实验技术研究PECVD沉积的a-Si:H薄膜的光学性质
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461495
Yudong Zhang, Xingyu Li, Jiale Tang, Yongjie Hu, Jie Yuan, Lulu Guan, H. Cui, Guanghui Ding, Xinying Shi, Kaidong Xu, Shiwei Zhuang
{"title":"Investigation of the optical properties of a-Si:H films deposited by PECVD using various experimental techniques","authors":"Yudong Zhang, Xingyu Li, Jiale Tang, Yongjie Hu, Jie Yuan, Lulu Guan, H. Cui, Guanghui Ding, Xinying Shi, Kaidong Xu, Shiwei Zhuang","doi":"10.1109/CSTIC52283.2021.9461495","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461495","url":null,"abstract":"In order to study the optical properties of hydrogenated amorphous silicon (a-Si:H) films prepared by plasma-enhanced chemical vapor deposition (PECVD), the influence of process parameters on the extinction coefficient (EC) and the refractive index(n) of a-Si:H films is investigated in the spectrum from 400 to 900 cm−1. The results show that the enhanced HF power and substrate temperature are the most important parameters for increasing the EC and n of the film.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126978256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research on Ultra-Precision Polishing Process of Semiconductor Wafer Surface Based on Disc Hydrodynamic Polishing 基于圆盘流体动力抛光的半导体晶圆表面超精密抛光工艺研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461534
JI Xiang-min, Jiang Xiaoxiong, Lin Bin, Cao Zhang-Chen
{"title":"Research on Ultra-Precision Polishing Process of Semiconductor Wafer Surface Based on Disc Hydrodynamic Polishing","authors":"JI Xiang-min, Jiang Xiaoxiong, Lin Bin, Cao Zhang-Chen","doi":"10.1109/CSTIC52283.2021.9461534","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461534","url":null,"abstract":"Nowadays, the fabrication of ultra-smooth surface play critical roles in, integrated circuits (IC) manufacturing, especially for semiconductor substrate materials of silicon, silicon dioxide and silicon carbide wafer. To efficiently production ultra-smooth semiconductor wafer surface, a novel Disc Hydrodynamic Polishing (DHDP) process is proposed. In DHDP process, the polishing slurry was injected from the center of polishing tool and a screw pressure groove was designed on the polishing pad. Then, the fluid film will be formed between the disc polishing pad and the wafer surface, under the high rotation speed and applied load of disc polishing tool. In the fluid film, the particles were droved by the hydrodynamic pressure and shear stress impact the wafer workpiece. The abrasive particles erode the workpiece under the hydrodynamic pressure in the fluid film. Then, the effect of tool speed and machining time on the quality of surface is studied, through a series of experiments. The rotational speed of polishing tool can improve the surface quality. The surface of fused quartz glass wafer surface roughness(Ra) could reach 0.7nm and the peak value(PV) is 8.9nm, which was polished by DHDP process. Moreover, DHDP process can efficiently reduce the surface roughness and acquire ultra-smooth surface for semiconductor wafer.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"56 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130317913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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