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Methods of Reducing Metal Damager Defect in Back End of Line for Semiconductor in 28Nm Technology 减少28Nm半导体后端金属损伤缺陷的方法
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461421
Shanshan Chen, Hungling Chen, Yin Long, Hao Guo, Kai Wang
{"title":"Methods of Reducing Metal Damager Defect in Back End of Line for Semiconductor in 28Nm Technology","authors":"Shanshan Chen, Hungling Chen, Yin Long, Hao Guo, Kai Wang","doi":"10.1109/CSTIC52283.2021.9461421","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461421","url":null,"abstract":"As technology keeps shrinking to 28nm and below, airborne molecular contamination has become a critical element of cleanroom management, which would influence the performance of device, but also decrease the yield and productivity in the semiconductor manufacturing process. As we know that in the Fab, wafers are always stored in the Front-Opening-Unified-Pod (FOUP) while waiting for process. The outgassing or contamination distribution within the FOUP has a strong negative impact on wafers. So additional precautions need to be taken to prevent external contamination during FOUP door opening or closing. This study investigated that metal damager defect appeared after the Cu electroplating (ECP) process in M1 feature structure. It was susceptible that Cu seed exposing to atmosphere was easy to be damaged by ambient gas. Here we illustrated two methods to reduce the metal damager defect. Firstly, Annealing process was applied before Buried Seed deposition, which could help remove the outgassing on the surface of wafer. Secondly, using the diffuser FOUP during the process of Via Etch to ECP process, and making sure the copper was in a super pure gas environment. The experiments consistently demonstrated that using diffuser FOUP and simultaneously introducing Annealing before Buried Seed could significantly improve metal damager defect.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121832040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
R2R Based Alternating Direction Method of Multi-Parameter Control Strategy 基于R2R的多参数交替方向控制方法
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461504
Huating Huang, Jingwen Ma, Chang Xu
{"title":"R2R Based Alternating Direction Method of Multi-Parameter Control Strategy","authors":"Huating Huang, Jingwen Ma, Chang Xu","doi":"10.1109/CSTIC52283.2021.9461504","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461504","url":null,"abstract":"In semiconductor industry, run-to-run (R2R) can strongly improve process performance by adjusting process parameters. Based on R2R algorithm, Alternating Direction Method is presented to deal with the multi-parameter control problem, especially problem with interaction terms. This method splits parameters into two parts, and updates each part's parameters by R2R algorithm respectively. Moreover by applying the control strategy for low pressure chemical vapor deposition (LPCVD) furnace process, the uniformity of wafer-to-wafer film thickness has been significantly improved.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123806533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer Defect Classification Based on DCNN Model 基于DCNN模型的晶圆缺陷分类
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461447
Pan Tian, Chen Li, Hao Fu, Xueru Yu, Zhengying Wei, Qiliang Ni, Xu Chen, Yunwei Ding, Ruojia Xu, Rui Sun
{"title":"Wafer Defect Classification Based on DCNN Model","authors":"Pan Tian, Chen Li, Hao Fu, Xueru Yu, Zhengying Wei, Qiliang Ni, Xu Chen, Yunwei Ding, Ruojia Xu, Rui Sun","doi":"10.1109/CSTIC52283.2021.9461447","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461447","url":null,"abstract":"Wafer defect classification is essential in semiconductor manufacturing for fast response of equipment and process stability monitoring, it is also critical for product yield management. Manual defect classification is time-consuming and prone to errors. This study presents an automatic defect classification (ADC) method based on a deep convolution neutral network (DCNN) model. The trained model has proven itself to be able to achieve defect classification performance sufficiently good to serve in the Fab.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130306671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Role of 1-H Carboxyl Benzotriazole as Corrosion Inhibitor for Cobalt “Bulk Step” Cmp in H2O2 Based Alkaline Slurry 1-H羧基苯并三唑在H2O2基碱性浆料中作为钴“体步”Cmp缓蚀剂的作用
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461582
Shuangshuang Lei, Chenwei Wang, Sheng-li Wang
{"title":"Role of 1-H Carboxyl Benzotriazole as Corrosion Inhibitor for Cobalt “Bulk Step” Cmp in H2O2 Based Alkaline Slurry","authors":"Shuangshuang Lei, Chenwei Wang, Sheng-li Wang","doi":"10.1109/CSTIC52283.2021.9461582","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461582","url":null,"abstract":"Cobalt has been considered as new interconnect metal. In this work, the passivation effect of 1-H Carboxyl Benzotriazole (CBT) on cobalt corrosion during “bulk step” chemical mechanical polishing (CMP) in H2O2 based alkaline slurry was investigated. The result showed that CBT can effectively inhibit the corrosion of cobalt and improve the surface quality after CMP by forming a passivation film on the cobalt surface. Characterization and analysis were given by potential polarization curves, X-ray photoelectron spectroscopy (XPS) and SEM measurements. Meanwhile, the passivation effect of CBT on cobalt was also verified from the mechanical aspect such as working pressure and carrier/platen speeds.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129189340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Manufacturing Process Optimization of Polycrystaline Aluminum and Aluminum Alloy on SiO2/Si SiO2/Si复合材料制备多晶铝及铝合金工艺优化
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461590
P. Zhang, Ping Huang, Z. Jin, C. Han
{"title":"Manufacturing Process Optimization of Polycrystaline Aluminum and Aluminum Alloy on SiO2/Si","authors":"P. Zhang, Ping Huang, Z. Jin, C. Han","doi":"10.1109/CSTIC52283.2021.9461590","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461590","url":null,"abstract":"Chlorine-based plasma of BCl3/CCl4 etc. was applied to dry-etch PVD sputtered 1.2µm aluminum alloy with Al-Si-Cu 98%-1%-1%. AZ-1500 resist acted as the etching mask for Al. XRD of alloy with annealing temperature of 300°C, 400°C on TEOS oxide and 20°C, 400°C on silicon, was reported. Etching away Al with bigger grain at the scribe lines, improved the dicing and decreased the cracking. Applying the chemical onto the developed i-line chemical amplified resist further decreased the optical CD to 0.15µm with the reticle CD 0.35µm. Newly obtained mask has the resist thickness of 2-5 µm with the slope of 89°. Oxygen plasma cleaning was applied. Optimized electromigration after high-temperature-annealing with bigger grain decreased both short circuitry (Hilllocks) for Ohmic contact and broken circuitry (Void) for interconnect.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117282949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Ternary Logic based on Reram Crossbars 基于Reram横杆的三元逻辑设计
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461521
Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang, Weikang Qian
{"title":"Design of Ternary Logic based on Reram Crossbars","authors":"Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang, Weikang Qian","doi":"10.1109/CSTIC52283.2021.9461521","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461521","url":null,"abstract":"Implementing logic within ReRAM crossbar is an attractive approach to overcome the memory wall in conventional von Neumann architectures. Compared to binary logic, the ternary logic can reduce area and power overhead with enhanced computing speed. In this paper, a ternary logic design based on ReRAM crossbars is proposed. Experimental results show that the proposed ternary logic gates have better performance in terms of switching speed, area, and power as compared to the previously published IMPLY and MAGIC designs.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interconnect-Centric Benchmarking of In-Memory Acceleration for DNNS 以互连为中心的DNNS内存加速基准测试
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461480
G. Krishnan, Sumit K. Mandai, C. Chakrabarti, Jae-sun Seo, U. Ogras, Yu Cao
{"title":"Interconnect-Centric Benchmarking of In-Memory Acceleration for DNNS","authors":"G. Krishnan, Sumit K. Mandai, C. Chakrabarti, Jae-sun Seo, U. Ogras, Yu Cao","doi":"10.1109/CSTIC52283.2021.9461480","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461480","url":null,"abstract":"In-memory computing (IMC) provides a dense and parallel structure for high performance and energy-efficient acceleration of deep neural networks (DNNs). The increased computational density of IMC architectures results in increased on -chip communication costs, stressing the interconnect fabric. In this work, we develop a novel performance benchmark tool for IMC architectures that incorporates device, circuits, architecture, and interconnect under a single roof. The tool assesses the area, energy, and latency of the IMC accelerator. We analyze three interconnect cases to illustrate the versatility of the tool: (1) Point-to-point (P2P) and network-on-chip (NoC) based IMC architectures to demonstrate the criticality of the interconnect choice; (2) Area and energy optimization to improve IMC utilization and reduce on-chip interconnect cost; (3) Evaluation of a reconfigurable NoC to achieve minimum on-chip communication latency. Through these studies, we motivate the need for future work in the design of optimal on-chip and off-chip interconnect fabrics for IMC architectures.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Economic Layout Solution with 20 UM Scribe Line and Integrated Test PAD Based on 55 NM Platform 基于55nm平台的20um划线线和集成测试PAD的经济布局解决方案
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461527
Yang Zhao, Chen Liang, Luchen, Jianning Deng, Liangliang He
{"title":"An Economic Layout Solution with 20 UM Scribe Line and Integrated Test PAD Based on 55 NM Platform","authors":"Yang Zhao, Chen Liang, Luchen, Jianning Deng, Liangliang He","doi":"10.1109/CSTIC52283.2021.9461527","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461527","url":null,"abstract":"In this work, an economic layout is designed for production of small sized chip with 20 um scribe line and integrated chip yield test pad. Three different kinds of layout are presented and thoroughly analyzed. Compared-with conventional 60 um scribe line layout, there is about 1 7% increase of chip quantity for a 20 um scribe line-layout with concentrated stacking mode of test key (TK) and marks. Such a novel layout maybe can be further expanded to different technology nodes and wafer size.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123202573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Non-Linear Resistive Switching Characteristics in HFO2-Based RRAM with Low-Dimensional Material Engineered Interface 基于低维材料工程界面的hfo2 RRAM的非线性电阻开关特性
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461454
Linbo Shan, Zongwei Wang, Lindong Wu, Shengyu Bao, Yi-Shao Chen, Kechao Tang, Yimao Cai, Ru Huang
{"title":"Non-Linear Resistive Switching Characteristics in HFO2-Based RRAM with Low-Dimensional Material Engineered Interface","authors":"Linbo Shan, Zongwei Wang, Lindong Wu, Shengyu Bao, Yi-Shao Chen, Kechao Tang, Yimao Cai, Ru Huang","doi":"10.1109/CSTIC52283.2021.9461454","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461454","url":null,"abstract":"Resistive switching devices with inherent nonlinear characteristics have great advantages in high density integration. In this paper, we demonstrated non-linear resistive switching behavior through engineering the interfacial layer with the low-dimensional hexagonal boron nitride(h-BN). The h-BN interface can act as a joint barrier to restrict ion-migration and modulate the carrier conduction due to its low diffusion rates. The experimental results show that the h-BN engineered devices exhibit excellent nonlinear properties in the low-resistance state and incremental analog behavior compared with the control samples owing to the h-BN diffusion limiting layer. The conduction mechanisms of both devices are demonstrated through experiments and theoretical analysis.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128377639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Isolated Word Speech Recognition based on BNN and Its Hardware Implementation 基于BNN的孤立词语音识别及其硬件实现
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461579
Xin Liu, Kefei Liu, Xiaoxin Cui, Yuan Wang
{"title":"Isolated Word Speech Recognition based on BNN and Its Hardware Implementation","authors":"Xin Liu, Kefei Liu, Xiaoxin Cui, Yuan Wang","doi":"10.1109/CSTIC52283.2021.9461579","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461579","url":null,"abstract":"In this paper, a binary convolution neural network (BNN) is proposed to realize isolated word speech recognition task, which greatly reduces the model training parameters and training time. For isolated word data sets, the rectangular convolution kernel is designed to replace the traditional square convolution kernel, and batch normalization layer is integrated into the convolution layer to realize the lossless acceleration of the inference process. The binary convolution neural network is deployed on FPGA to realize the edge calculation.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131373100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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