2021 China Semiconductor Technology International Conference (CSTIC)最新文献_第7页

The Setting of Linewidth Reference on Photomasks through Physical Process Modeling 基于物理过程建模的光掩模线宽参考的设置

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461528

Rui Hu, Qiang Wu

{"title":"The Setting of Linewidth Reference on Photomasks through Physical Process Modeling","authors":"Rui Hu, Qiang Wu","doi":"10.1109/CSTIC52283.2021.9461528","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461528","url":null,"abstract":"The use of photomask can maximally realize the power of parallel pattern replication in photolithography. Although there exists linewidth standard in the metrology tools, in practice, there may exists some variation in the linewidth definition from different chip makers. Experience indicates that such variation can be as much as 1~2 nm (1X). Since the mask bias can affect photo process window, the determination of which can be very important to the setup of the lithography process. Of course, the optimum setting can be obtained through wafer exposure. However, ever since the introduction of Model Based Optical Proximity Correction (MBOPC), the linewidth uniformity across different patterns is mostly accomplished by OPC model and correction. Therefore, it is important that the mask dimension be as close to the reality as possible to make OPC model more physical, which have better extendibility to patterns that may lie along the edge of the design rules or even slightly outside the design rules. Ever since the use of 193 nm immersion lithography, the mask dimension may be very close to the size of the wavelength, mask 3D scattering effect becomes very significant, which can reduce imaging contrast, increase Mask Error Factor (MEF), and reduce common Depth of Focus (DoF) for all patterns. The setting of the accurate mask dimension becomes more important, even critical. However, we can also utilize this process window sensitivity to the mask dimension to determine the real mask dimension through comparing wafer exposure data and simulation. This will require very accurate physical modeling. In this paper, we will propose this method.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129519461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Effects of Poly Corner Etch Residue on Advanced Finfet Device Performance 聚角蚀刻残留物对先进finet器件性能的影响

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461583

Qingpeng Wang, Yu De Chen, Cheng Li, Rui Bao, Jacky Huang, J. Ervin

引用次数: 0

Chemical Mechanical Polishing of Semiconductor Wafers: Surface Element Modeling and Simulation To Predict Wafer Surface Shape 半导体晶圆的化学机械抛光:表面元建模与模拟以预测晶圆表面形状

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461553

Qi Zhang, Zhen Li, H. Qi, Zhichao Li

引用次数: 0

Board-Level Thermal Cycle Simulation and Improvement of 2.5D Large-Size Package 2.5D大尺寸封装板级热循环仿真及改进

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461444

Shi-Yew Chen, Dan-Liang Yang, Na Mei, Tuobei Sun, Keqing Ouyang

引用次数: 2

The Failure Mechanism of Drain Bias TDDB and Characterization of Lifetime Model for HV Depmos 高压电容器漏极偏置TDDB失效机理及寿命模型表征

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461439

Xiumei Song, Weihai Fan, Xiaobo Duan, Qingyuan Qin

引用次数: 0

Next Generation Test Library for RF SOC on ATE 下一代射频SOC测试库

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461580

Ping Wang, Haocheng Yuan, Vincent Lin, Haixia Guo, Goh. Frank

{"title":"Next Generation Test Library for RF SOC on ATE","authors":"Ping Wang, Haocheng Yuan, Vincent Lin, Haixia Guo, Goh. Frank","doi":"10.1109/CSTIC52283.2021.9461580","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461580","url":null,"abstract":"Current RF SOC devices are highly complex with many modules with different functions and wireless standards. This complexity results in thousands of tests needed even for production testing. Characterization and engineering test flow will demand even more tests. It takes a lot of time to develop, debug and bring the program into production. This is especially true for new engineers which can take months or years to develop on their own. Typical solution would be to develop a test library to generate all the tests. However, not all test library are build the same. And typical” 1st generation” are done to get the job done. They can be difficult to debug and may need hack codes for special or customized test. In addition, some libraries have grown so complex that it takes a long time to learn how to use them. With experiences gained from development of many projects and Java coding, a new better next generation test library was developed. This paper described a new improved version of such a test library which provides more features & benefits, more user friendly and easy to learn. The paper first describes the need for test library and typical issues with existing test libraries. The benefits and new features of the next generation test library will be introduced. The structure and use model of this user-friendly RF SOC test library will be described. How and why development time and cost will be reduced. Complicated hacking codes can be eliminated. Future-proofing the library, it is designed to allow new wireless standards and tests to be added. Debugging and setup features will also be described. Efficient and ease of importing user input, registers setup and design pattern will help even new users create test program efficiently and quickly. This library is also designed to ease learning curve when using it. A beginner can develop a new kind of RF SOC offline program within one month. Framework to allow easy usage allows users to stay at a higher level helps them to focus on test strategies.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116833909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

SEM Image Transformation Between Litho Domain and Etch Domain 光刻域与蚀刻域之间的SEM图像变换

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461458

Yan Yan, X. Shi, Chen Li, Bowen Xu, Yifei Lu, Ying Gao, Wenzhan Zhou, Kan Zhou

{"title":"SEM Image Transformation Between Litho Domain and Etch Domain","authors":"Yan Yan, X. Shi, Chen Li, Bowen Xu, Yifei Lu, Ying Gao, Wenzhan Zhou, Kan Zhou","doi":"10.1109/CSTIC52283.2021.9461458","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461458","url":null,"abstract":"In semiconductor manufacturing, a forward etching process model that can accurately predict the pattern transformation from post-lithography (ADI) to post-etch (AEI) is greatly desired. However, current etching model is etch bias based, it is unable to offer rich information as the SEM image does for engineers to do wafer disposition. In practice, ambiguous circumstances often arise when a disposition decision cannot be made easily by examining the post-lithography pattern image alone. The probability of making the disposition decision correctly can be greatly enhanced if the post etch image can be predicted accurately. Likewise, an inverse etching model that can predict post lithography pattern SEM image from post-etch pattern SEM image is also desired for OPC lithography target layer definition. Current OPC lithography target layer is derived from etch bias estimation from a forward etching model. The rigorous solution to OPC lithography target layer generation should come from an inverse etching model instead of the forward etching model. These practical needs have motivated us to develop models that can transform SEM images between post lithography domain and post etch domain freely and accurately. In this paper, we will report results from our proposed image based forward etching model and the image based inverse etching model. The deep convolutional neural network (DCNN) models have achieved SEM image transformation between post lithography and post etch accurately enough for practical applications.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114447797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The Strong Effect of Spectral Mode and Directional Electrical Field for Nuisance Filtering In Defect Inspection 光谱模式和方向电场对缺陷检测中滋扰滤波的强作用

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461546

Xingdi Zhang, Hungling Chen, Yin Long, Kai Wang

引用次数: 0

Advance manufacturing process of LCOS based on Copper Reflector 基于铜反射器的LCOS先进制造工艺

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461558

Zhao Guo

引用次数: 1

A Study of Inter-Via CD and PEB Amount Correlation in Dual Damascene Process 双大马士革过程中通孔间CD与PEB量相关性研究

2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461471

Xinruo Su, Xuebing Zhao, Yuan Li, Jun Wang

引用次数: 0