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A Low-Bit Quantized and HLS-Based Neural Network FPGA Accelerator for Object Detection 一种基于hls的低比特量化神经网络FPGA目标检测加速器
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461256
Jiaming Huang, Junyan Yang, Saisai Nui, Hang Yi, Wei Wang, Hai-Bao Chen
{"title":"A Low-Bit Quantized and HLS-Based Neural Network FPGA Accelerator for Object Detection","authors":"Jiaming Huang, Junyan Yang, Saisai Nui, Hang Yi, Wei Wang, Hai-Bao Chen","doi":"10.1109/CSTIC52283.2021.9461256","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461256","url":null,"abstract":"In this paper, a HLS-based convolutional neural network (CNN) accelerator is designed for FPGA and channel-wise low-bit quantization is applied to YOLOv3- Tiny, whose weights are quantized to 2-bit while activations are quantized to 8-bit. The quantization range is learnable in training to prevent severe accuracy loss. The accelerator uses sliding window technique to improve data reusability and efficient process element (PE) is designed to utilize low-bit calculation. This design makes full use of DSP and LUT resources and exploits optimal parallelism on embedded FPGA. The performance of our design can reach 90.6 GOP/s on PYNQ-Z2 at 150 MHz, which outperforms other accelerators implemented on the same platform in terms of peak performance and power efficiency.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Effect of TTA-K as Inhibitor On CU/RU/TAN Structure based Patterned Wafer CMP TTA-K作为抑制剂对CU/RU/TAN结构的图像化晶圆CMP的影响
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461442
Yuan Tian, Chenwei Wang, Jianwei Zhou, Chen-cong Xu, Xue Zhang, Chao Wang
{"title":"Effect of TTA-K as Inhibitor On CU/RU/TAN Structure based Patterned Wafer CMP","authors":"Yuan Tian, Chenwei Wang, Jianwei Zhou, Chen-cong Xu, Xue Zhang, Chao Wang","doi":"10.1109/CSTIC52283.2021.9461442","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461442","url":null,"abstract":"The inhibitor added into the slurry during copper/barrier chemical mechanical planarization (CMP) plays a vital role in controlling the dishing and erosion of the patterned wafer. In this paper, a kind of corrosion inhibitor TTA-K was introduced in H2O2 based alkaline slurry. The experimental results showed that the addition of TTA-K can effectively reduce the removal rate (RR) and static etch rate (SER) of Cu. The results revealed that with the increase of TTA-K concentration, the passivation effect was enhanced. The dishing and erosion test results showed that the TTA - K can effectively reduce the depth of dishing and erosion with different line widths and spaces. Electrochemistry, XPS and SEM measurement was implemented to characterize the mechanism of TTA-K passivation.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132060393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Lithographic Simulator Based on Deep Learning with Graph Input 基于图形输入深度学习的光刻模拟器
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461424
Peng Xu, Pengpeng Yuan, Yayi Wei
{"title":"Lithographic Simulator Based on Deep Learning with Graph Input","authors":"Peng Xu, Pengpeng Yuan, Yayi Wei","doi":"10.1109/CSTIC52283.2021.9461424","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461424","url":null,"abstract":"This paper discuss a simple deep neural network which aimed to finish the simulation of the lithographic process. It can be finalized by a more comprehensive model formed by combined networks each for different parts of lithographic process. The advantage of the DNN is that it uses a graph input as the representation of the layout. As a result it can be easily combined with the current industrial software. Furthermore, this DNN can be applied reversely to generate a regularized pattern from data of current commercial ILT package. It will at least improve the manufacturability of ILT results generated by the current commercial package.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123882959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Preparation of ZNO Doped SiO2 Abrasive and Chemical Mechanical Polishing Performance on C-Plane Sapphire Substrate ZNO掺杂SiO2磨料的制备及C-Plane蓝宝石衬底的化学机械抛光性能
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461254
Ziyang Hou, X. Niu, Yanan Lu, Yinchan Zhang, Yebo Zhu, Yangang He
{"title":"Preparation of ZNO Doped SiO2 Abrasive and Chemical Mechanical Polishing Performance on C-Plane Sapphire Substrate","authors":"Ziyang Hou, X. Niu, Yanan Lu, Yinchan Zhang, Yebo Zhu, Yangang He","doi":"10.1109/CSTIC52283.2021.9461254","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461254","url":null,"abstract":"Sapphire substrate is the most commonly used in semiconductor industry for GaN-based light emitting diodes (LEDs). Chemical mechanical polishing (CMP) is one of the most effective methods to achieve atomic-scale smooth surface. Sapphire is very difficult to process due to its brittleness and high hardness. In order to improve the processing efficiency of sapphire CMP, ZnO was used as an additive in this paper. Because of the insolubility of ZnO in the slurry, the effect of ZnO on the removal rate is not obvious. Through the preparation process optimization of mixing surfactant, deionized water and ZnO with ultrasonic dispersion, the dispersion effect of ZnO in sapphire slurry was obviously enhanced, and the CMP processing efficiency of sapphire substrate was effectively improved. Meanwhile, the action mechanism of ZnO was investigated in depth.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124077846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Dynamic Sampling Algorithm Based on Cosrisk Assessment Model in Semiconductor Manufacturing 半导体制造中基于成本风险评估模型的动态采样算法
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461450
Sen Wang, Shijia Yan, Lei Li, Cong Luo, Juan Ai, Qiang Shen, Desheng Wang, Shenglan Ding, Qing Xia
{"title":"A Dynamic Sampling Algorithm Based on Cosrisk Assessment Model in Semiconductor Manufacturing","authors":"Sen Wang, Shijia Yan, Lei Li, Cong Luo, Juan Ai, Qiang Shen, Desheng Wang, Shenglan Ding, Qing Xia","doi":"10.1109/CSTIC52283.2021.9461450","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461450","url":null,"abstract":"Traditional fixed sampling methods are becoming more difficult to meet the requirements of today's advanced semiconductor manufacturing. In this paper, we propose a dynamic sampling algorithm based on a cost-risk assessment model. According to the result of application, the algorithm not only effectively reduces the sample ratio and the cycle time, but also reduces the catch excursion of the required number of sampling lots and interval time. It can improve the economic efficiency of measurement per unit time and further improve the production capacity of the enterprise.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128792264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HNA Wet Etching Optimization in Wafer Thinning of BSI Process BSI晶圆减薄工艺中的HNA湿法蚀刻优化
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461419
Pengfei Lyu, Min Xiang, Jia Xu, Tianhao Zhang, Quan Zhang, Qingpeng Zhao
{"title":"HNA Wet Etching Optimization in Wafer Thinning of BSI Process","authors":"Pengfei Lyu, Min Xiang, Jia Xu, Tianhao Zhang, Quan Zhang, Qingpeng Zhao","doi":"10.1109/CSTIC52283.2021.9461419","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461419","url":null,"abstract":"In order to achieve higher quantum efficiency and sensitivity of image sensor, the Backside-Illumination (BSI) has been developed by turning FSI's metal wiring and photosensitive area upside down. Together with the benefits, a series of new challenges are also brought along with this new technology. Among them, how to achieve uniform wafer thinning has become a critical issue for wet clean process. This paper focuses on wet etching optimization of HNA, the chemical applied in wafer thinning process. With help of advanced Lam Research SP323 single wafer clean hardware and software, an improved wafer thinning performance throughout long-time running can be achieved.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SI3N4 Plasma Etch Study for Optimized Morphology Performance 优化形貌性能的SI3N4等离子蚀刻研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461506
Quanbao Li, Xiaohui Ren, Jihong Zhang, Y. Chi
{"title":"SI3N4 Plasma Etch Study for Optimized Morphology Performance","authors":"Quanbao Li, Xiaohui Ren, Jihong Zhang, Y. Chi","doi":"10.1109/CSTIC52283.2021.9461506","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461506","url":null,"abstract":"Si<inf>3</inf>N<inf>4</inf> etch control is one of the most critical processes for profile angle, uniformity and selectivity. We investigated the morphology and selectivity of Si<inf>3</inf>N<inf>4</inf> etch in inductively coupled plasmas (ICP) and capacitively-coupled plasmas (CCP), which are standardly used in fabrication industry for the etching process with Lam conductor etch (CE) Kiyo<sup>®</sup> series and dielectric etch (DE) Flex<sup>®</sup> series tool, respectively. In our study, Si<inf>3</inf>N<inf>4</inf> etching was performed by using CF<inf>4</inf>/CHF<inf>3</inf>based plasma and combining O<inf>2</inf> plasma to balance passivation when mixed with diluted gas AR or helium. We have focused on tuning ESC temperature, O<inf>2</inf> flow, total flow, gas ratio and power splits to improve profile angle and uniformity. In addition, the wafer edge tilting issue has also been optimized to improve extreme edge profile tilting process window in extreme edge area.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124142274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Millimeter Wave Transceiver Isolation System Based on Polarization Converter and Grating 基于偏振变换器和光栅的毫米波收发隔离系统设计
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461481
Jiabing Liu, Ke Wang, Yaozu Guo, X. Ji, Ping Han, Feng Yan, Y. Liao
{"title":"Design of Millimeter Wave Transceiver Isolation System Based on Polarization Converter and Grating","authors":"Jiabing Liu, Ke Wang, Yaozu Guo, X. Ji, Ping Han, Feng Yan, Y. Liao","doi":"10.1109/CSTIC52283.2021.9461481","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461481","url":null,"abstract":"In this paper, a millimeter wave transceiver isolation system integrated with polarization converter and grating is designed by quasi optical method. The polarization converter is composed of double-layer substrates, each of one is 200 µm thick quartz glass with a layer of metasurface structures on its surface. Besides, the grating is designed and optimized on a 0.1 mm thick copper sheet. The simulation and calculation results show that the isolation is higher than 20 dB and the transmission loss is lower than 0.85 dB and the receiving loss is lower than 1 dB at 72 – 82 GHz.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125691848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stochastic Circuit Design Based on Exact Synthesis 基于精确综合的随机电路设计
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461462
Xiang He, Zhufei Chu
{"title":"Stochastic Circuit Design Based on Exact Synthesis","authors":"Xiang He, Zhufei Chu","doi":"10.1109/CSTIC52283.2021.9461462","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461462","url":null,"abstract":"Stochastic computing enables computationally complex arithmetic using binary numbers converted to stochastic bitstreams. A large number of applications have used stochastic computing due to its fault-tolerant nature. However, stochastic circuit synthesis presents a larger solution space when compared to classical logic synthesis. Previous methods synthesize stochastic circuits using a heuristic method. In this paper, a novel exact synthesis method using Boolean satisfiability (SAT) is proposed to obtain an optimal stochastic circuit represented by majority-inverter graphs (MIGs). The experimental results suggest that the proposed approach can achieve 21% area reduction, 4% delay improvement, with a 3% mean absolute error trade-off.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130605500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Study of Thermal Interface Materials with Different Thermal Conductivity for HFCBGA Package 不同导热系数的HFCBGA封装热界面材料研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461502
Feng Wang, Na Mei, Yuanting Lai, Tuobei Sun, Keqing Ouyang
{"title":"A Study of Thermal Interface Materials with Different Thermal Conductivity for HFCBGA Package","authors":"Feng Wang, Na Mei, Yuanting Lai, Tuobei Sun, Keqing Ouyang","doi":"10.1109/CSTIC52283.2021.9461502","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461502","url":null,"abstract":"As the chip integration level increases and the chip power consumption density increases, reducing the internal thermal resistance of package becomes the main consideration of thermal design. Currently, the widely used HFCBGA is a thermally enhanced FCBGA mounting a metal heat spreader on the back of the chip through thermal interface materials(TIM), which is applied with various high-heat-conducting filler. Selecting a highly thermally conductive TIM is already a key thermal performance index to reduce thermal resistance of junction to case. Through these series of studies, We found that one TIM material is an effective method to solve the heat dissipation problem and have also been qualification.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"3 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120912655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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