A Low-Bit Quantized and HLS-Based Neural Network FPGA Accelerator for Object Detection

Abstract

In this paper, a HLS-based convolutional neural network (CNN) accelerator is designed for FPGA and channel-wise low-bit quantization is applied to YOLOv3- Tiny, whose weights are quantized to 2-bit while activations are quantized to 8-bit. The quantization range is learnable in training to prevent severe accuracy loss. The accelerator uses sliding window technique to improve data reusability and efficient process element (PE) is designed to utilize low-bit calculation. This design makes full use of DSP and LUT resources and exploits optimal parallelism on embedded FPGA. The performance of our design can reach 90.6 GOP/s on PYNQ-Z2 at 150 MHz, which outperforms other accelerators implemented on the same platform in terms of peak performance and power efficiency.