Stochastic Circuit Design Based on Exact Synthesis

Abstract

Stochastic computing enables computationally complex arithmetic using binary numbers converted to stochastic bitstreams. A large number of applications have used stochastic computing due to its fault-tolerant nature. However, stochastic circuit synthesis presents a larger solution space when compared to classical logic synthesis. Previous methods synthesize stochastic circuits using a heuristic method. In this paper, a novel exact synthesis method using Boolean satisfiability (SAT) is proposed to obtain an optimal stochastic circuit represented by majority-inverter graphs (MIGs). The experimental results suggest that the proposed approach can achieve 21% area reduction, 4% delay improvement, with a 3% mean absolute error trade-off.