发布求助
文献互助 智能选刊 最新文献

2021 China Semiconductor Technology International Conference (CSTIC)最新文献

筛选
英文 中文
Research on the Thermal Reliability of Multi-Unit Power Integrated Module 多单元电源集成模块热可靠性研究
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461437
Juan Hu, J. Bao, Li Wang, Shan Lu
{"title":"Research on the Thermal Reliability of Multi-Unit Power Integrated Module","authors":"Juan Hu, J. Bao, Li Wang, Shan Lu","doi":"10.1109/CSTIC52283.2021.9461437","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461437","url":null,"abstract":"Multi-unit IGBT PIM (Power Integrated Module) is widely used in industrial transmission and household air conditioning due to its small size, light weight and low switching loss. More and more attention is paid to its reliability. Through a simulation study, the package structure of a PIM with a three-phase bridge rectifier, a chopper and a three-phase IGBT module was analyzed. Due to the limitation of package structure, chopper circuit works at the highest temperature. By comparing the temperature distribution of a SiC hybrid PIM using SiC Schottky barrier diodes instead of Si fast recovery diodes with the original Si-PIM, the chip layout and vertical packaging structure of the SiC hybrid PIM are optimized. The high thermal conductivity material such as graphene was applied to the PIM to improve the thermal reliability performance. After optimization, the maximum temperature of the module can drop by 24°C.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130032859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Nonlinear Quantization for In-Sram Multi-Bit MAC Design sram内多比特MAC设计的非线性量化
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461589
Shuo Chen, Xudong Lu, Z. Pang, Shaodi Wang, Cheng Zhuo, Xunzhao Yin
{"title":"Nonlinear Quantization for In-Sram Multi-Bit MAC Design","authors":"Shuo Chen, Xudong Lu, Z. Pang, Shaodi Wang, Cheng Zhuo, Xunzhao Yin","doi":"10.1109/CSTIC52283.2021.9461589","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461589","url":null,"abstract":"In-memory computing arises as a novel computing paradigm aiming to overcome the memory wall bottleneck present in the conventional von Neumann architecture. By integrating the computation within the memory array, i.e., 6T CMOS SRAM array, in-memory computing blocks reduce the time- and energy-consuming data movement between the storage and processing cores, thus improving the energy efficiency and performance. Prior work [1] has focused on realizing the multi-bit multiplication and accumulation (MAC) in-memory operation by quantizing the analog discharge behavior associated with the SRAM bit cell. However, prior work realizes the multi-bit quantization by assuming that the discharge rate is linear to input voltage given a discharge interval. Such overlooking of the discharge nonlinearity associated with SRAM may hinder the design from practical multi-bit quantization. In this paper, we analyze the nonlinearity effect of the SRAM bit cell discharge and propose three optimization guidelines to address the challenges caused by nonlinear discharge. Simulation results validate our proposed methods.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of Supply Noise on Nano-Meter VLSI Design: Hard or Soft Threshold? 电源噪声对纳米级VLSI设计的影响:硬阈值还是软阈值?
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461455
Chenyi Wen, Yue Cai, Cheng Zhuo
{"title":"Impact of Supply Noise on Nano-Meter VLSI Design: Hard or Soft Threshold?","authors":"Chenyi Wen, Yue Cai, Cheng Zhuo","doi":"10.1109/CSTIC52283.2021.9461455","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461455","url":null,"abstract":"With VLSI keeps scaling down, power supply noise margin gets further diminished due to the relatively stable threshold voltage. On the other hand, the continuously growing current density incurs additional supply noise, which easily violates the pre-set power integrity noise margin threshold. Thus, power integrity (PI) designers have to either conduct repeated back-tracking or add additional die area to reduce the unwanted supply noise, which is both cost and time consuming. A very natural question that may arise is then what happens if this noise margin threshold is violated? In this paper, we will investigate the impact of supply noise on various designs for nano-meter VLSI and discuss the potential opportunities that may provide PI designers with additional design flexibility.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Universal Semiconductor ATPG Solutions for ATE Platform under the Trend of AI and ADAS 通用半导体在AI和ADAS趋势下的ATE平台ATPG解决方案
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461259
Qimeng Wang, Zhonghe. Tian, Xi. He, Ziteng. Xu, Mingjie. Tang, Shenqi. Cai, Wei. Zong
{"title":"Universal Semiconductor ATPG Solutions for ATE Platform under the Trend of AI and ADAS","authors":"Qimeng Wang, Zhonghe. Tian, Xi. He, Ziteng. Xu, Mingjie. Tang, Shenqi. Cai, Wei. Zong","doi":"10.1109/CSTIC52283.2021.9461259","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461259","url":null,"abstract":"This article introduces a universal semiconductor Automatic Test Pattern Generation (ATPG) solution for Automated Test Equipment (ATE) platform. With the increasing trend of Artificial Intelligence (AI) and Advanced Driving Assistance System (ADAS) the communication between semiconductor devices requires advanced protocols such as Mobile Industry Processor Interface (MIPI) and Point-to-point (P2P) protocols. A designer-based solution is developed to provide a one-click software approach to create test vectors for common protocols and customized protocols. As a result, the silicon debug cycle can be massively reduced, comparing with converting waveform files generated from traditional Electronic Design Automation (EDA) tools. This solution can dramatically reduce the workload of test engineers and enable IC designers to participate in the debugging process of the device directly with an intuitive way. Such workflow can rise the efficiency of semiconductor test process and further decrease the Time to Market (TTM) of new product. This solution is designed as a comparable tool towards traditional EDA tools and will be another choice for ATPG solution. Up to now, this solution can generate test vectors for advanced protocols like MIPI D-PHY/C-PHY as well as basic protocols such as Inter-Integrated Circuit (I2C) and Serial Peripheral Interface (SPI) and complete evaluation on real device.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121951897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mining Lithography Hotspots from Massive SEM Images Using Machine Learning Model 利用机器学习模型从大量扫描电镜图像中挖掘光刻热点
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461533
Tao Zhou, Bowen Xu, Chen Li, Xuling Diao, Yan Yan, Shoumian Chen, Yuhang Zhao, Kan Zhou, Wenzhan Zhou, Xuan Zeng, X. Shi
{"title":"Mining Lithography Hotspots from Massive SEM Images Using Machine Learning Model","authors":"Tao Zhou, Bowen Xu, Chen Li, Xuling Diao, Yan Yan, Shoumian Chen, Yuhang Zhao, Kan Zhou, Wenzhan Zhou, Xuan Zeng, X. Shi","doi":"10.1109/CSTIC52283.2021.9461533","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461533","url":null,"abstract":"An effect method based on machine learning is developed for hotspots mining in lithography. A series of models are trained independently and combined to achieve high accuracy. Innovatively, contour information is firstly adopted to assist the hotspot detection, which eases the very challenging task of detection for topology aberration caused by complicated process effects. More importantly, the proposed method based on new methodology provides high efficiency which is competent for high volume manufacturing.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126568534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Si/SnS2 Vertical Heterojunction Tunneling Transistor with Ionic-Liquid Gate for Ultra-Low Power Application 超低功耗离子-液体栅Si/SnS2垂直异质结隧道晶体管
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461446
Liang Chen, Rundong Jia, Qianqian Huang, Ru Huang
{"title":"Si/SnS2 Vertical Heterojunction Tunneling Transistor with Ionic-Liquid Gate for Ultra-Low Power Application","authors":"Liang Chen, Rundong Jia, Qianqian Huang, Ru Huang","doi":"10.1109/CSTIC52283.2021.9461446","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461446","url":null,"abstract":"In this work, a novel Si/SnS2 vertical heterojunction tunneling transistor (HTFET) with ionic-liquid gate is proposed and experimentally demonstrated. Si/SnS2 tunnel junction behaves nearly-broken band alignment with effective tunneling potential height of only 0.17 eV, which is beneficial for the on-state current. Besides, due to the mature doping and contact technology of Si, excellent contacts between Si/SnS2 and metal electrodes can be achieved. Moreover, the organic electrolyte (PEO: LiClO4=9: 1) is adopted as ionic-liquid gate stack and the electric double-layer structure formed by the anion and cation migration in the organic electrolyte can enhance the electrostatic control and optimize the subthreshold swing of the device.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126900772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Bi Content on the Microstructure and Mechanical Properties of CU/SN-XBI/CU Solder Joints After Soldering and Aging Bi含量对CU/SN-XBI/CU焊点焊接和时效后组织和力学性能的影响
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461460
Mingliang L. Huang, Renyong Wu, Jing Ren
{"title":"Effect of Bi Content on the Microstructure and Mechanical Properties of CU/SN-XBI/CU Solder Joints After Soldering and Aging","authors":"Mingliang L. Huang, Renyong Wu, Jing Ren","doi":"10.1109/CSTIC52283.2021.9461460","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461460","url":null,"abstract":"Five low-temperature Sn-xBi solder alloys were designed by the cluster-plus-glue-atom (CPGA) model. The effect of Bi content on the microstructure and mechanical properties of Cu/Sn-xBi/Cu solder joints under soldering and aging were investigated. As the Bi content reduced, the networked eutectic structure gradually disappeared, and the melting point of Sn-xBi solders increased. The interfacial intermetallic compounds (IMCs) increased with the aging time. After aging for 800 h, Bi segregation was observed at the Cu3Sn/Cu interface of the Sn-56.91Bi and Sn-46.81Bi solder joints. Bi segregation at the Cu3Sn/Cu interface decreased as Bi content decreased, and both the shear strength and ductility of Sn-xBi solder joints increased.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Etch Back Before ILD-CMP for Improving the Loading Issue after ILD-CMP 在ILD-CMP之前蚀刻回，以改善ILD-CMP之后的加载问题
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461490
Yangyang Dong, Junjie Zhang, K. Guo, Wei Zhang, Haifeng Zhou, J. Fang, Yu Zhang
{"title":"Etch Back Before ILD-CMP for Improving the Loading Issue after ILD-CMP","authors":"Yangyang Dong, Junjie Zhang, K. Guo, Wei Zhang, Haifeng Zhou, J. Fang, Yu Zhang","doi":"10.1109/CSTIC52283.2021.9461490","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461490","url":null,"abstract":"Inter-level dielectric chemical mechanical polishing (ILD CMP) technology has become one of the crucial technologies in integrated circuit which can contribute to the subsequent interconnections of metal and lithography processes. There is a step height between the gate scribe line and dense line which because of the gate and the higher gate is, the bigger step height is. The loading issue will not suffer after ILD CMP when the step height is within a certain range [1]. However, the gate must be very high or even twice as much due to process performance needs in 38 supper flash. In this situation, there will be a serious loading issue after ILD CMP. This paper will present how to improve loading with both etch-back and ILD CMP. Experiment results shown that there is no loading after ILD CMP when add etch-back process before ILD CMP.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"1931 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129028820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CNN Accelerator with Embedded Risc-V Controllers 嵌入式Risc-V控制器的CNN加速器
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461576
Li Zhang, Xian Zhou, Chuliang Guo
{"title":"A CNN Accelerator with Embedded Risc-V Controllers","authors":"Li Zhang, Xian Zhou, Chuliang Guo","doi":"10.1109/CSTIC52283.2021.9461576","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461576","url":null,"abstract":"Convolutional Neural Network is a promising technology in machine learning. Due to its vast computing and data requirements, it needs to be run with a specific accelerator to achieve reasonable energy efficiency. Improving the performance of accelerators has become the research hotspot. A mixed-precision structure can be used to improve hardware utilization, thus reducing area and power. However, the mixed-precision flow control is so complicated that it costs too much hardware resources. In this paper, a CNN accelerator with embedded RISC-V controllers is introduced to achieve flexible control at a very low cost. The ASIC synthesized results show that the proposed design area with two embedded cores is 5% less than the basic design.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116767065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Release Process Development for MEMS Micro-Bridge Structure MEMS微桥结构释放工艺开发
2021 China Semiconductor Technology International Conference (CSTIC) Pub Date : 2021-03-14 DOI: 10.1109/CSTIC52283.2021.9461441
Bo Zhang, Xiaoxu Kang, Xiaolan Zhong
{"title":"Release Process Development for MEMS Micro-Bridge Structure","authors":"Bo Zhang, Xiaoxu Kang, Xiaolan Zhong","doi":"10.1109/CSTIC52283.2021.9461441","DOIUrl":"https://doi.org/10.1109/CSTIC52283.2021.9461441","url":null,"abstract":"In this work, release process was developed for micro-bridge structure based MEMS products. Etch rate of release process for different material on blanket wafer was collected, and optimized thin film stack was obtained according to the data. Dedicated structure and MEMS product were then designed to evaluate the release process. From the physical data measured by 3D profiler, release process can well match the MEMS product requirements.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132534882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信