2.5D大尺寸封装板级热循环仿真及改进

Shi-Yew Chen, Dan-Liang Yang, Na Mei, Tuobei Sun, Keqing Ouyang
{"title":"2.5D大尺寸封装板级热循环仿真及改进","authors":"Shi-Yew Chen, Dan-Liang Yang, Na Mei, Tuobei Sun, Keqing Ouyang","doi":"10.1109/CSTIC52283.2021.9461444","DOIUrl":null,"url":null,"abstract":"A three-dimensional numerical model of 2.5D package is established, and a thermo-mechanical simulation is conducted to evaluate the board-level thermal cycle (BTC) behavior. When the coefficient of thermal expansion (CTE) is well matched between printed ciruit board (PCB) and substrate, the most risky solder ball is located at the middle side of narrow ring rather than the corner; While the CTE difference is large, the risky area changes to package corner. In order to make a deep understanding, the design of experiment (DOE) test is carried out to investigate the impact of parameters on the solder, which also provides theoretical guidance on improving the board-level interconnect reliability.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Board-Level Thermal Cycle Simulation and Improvement of 2.5D Large-Size Package\",\"authors\":\"Shi-Yew Chen, Dan-Liang Yang, Na Mei, Tuobei Sun, Keqing Ouyang\",\"doi\":\"10.1109/CSTIC52283.2021.9461444\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A three-dimensional numerical model of 2.5D package is established, and a thermo-mechanical simulation is conducted to evaluate the board-level thermal cycle (BTC) behavior. When the coefficient of thermal expansion (CTE) is well matched between printed ciruit board (PCB) and substrate, the most risky solder ball is located at the middle side of narrow ring rather than the corner; While the CTE difference is large, the risky area changes to package corner. In order to make a deep understanding, the design of experiment (DOE) test is carried out to investigate the impact of parameters on the solder, which also provides theoretical guidance on improving the board-level interconnect reliability.\",\"PeriodicalId\":186529,\"journal\":{\"name\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC52283.2021.9461444\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC52283.2021.9461444","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

建立了2.5D封装的三维数值模型,并对其板级热循环(BTC)行为进行了热-力学模拟。当印刷电路板(PCB)与基板之间的热膨胀系数(CTE)匹配良好时,最危险的焊球位于窄环的中间而不是角落;当CTE差异较大时,危险区域变为封装角。为了深入了解,实验设计(DOE)进行测试调查参数对焊接的影响,同时也提高董事会层面的互连的可靠性提供了理论指导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Board-Level Thermal Cycle Simulation and Improvement of 2.5D Large-Size Package
A three-dimensional numerical model of 2.5D package is established, and a thermo-mechanical simulation is conducted to evaluate the board-level thermal cycle (BTC) behavior. When the coefficient of thermal expansion (CTE) is well matched between printed ciruit board (PCB) and substrate, the most risky solder ball is located at the middle side of narrow ring rather than the corner; While the CTE difference is large, the risky area changes to package corner. In order to make a deep understanding, the design of experiment (DOE) test is carried out to investigate the impact of parameters on the solder, which also provides theoretical guidance on improving the board-level interconnect reliability.
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