Interconnect-Centric Benchmarking of In-Memory Acceleration for DNNS

Abstract

In-memory computing (IMC) provides a dense and parallel structure for high performance and energy-efficient acceleration of deep neural networks (DNNs). The increased computational density of IMC architectures results in increased on -chip communication costs, stressing the interconnect fabric. In this work, we develop a novel performance benchmark tool for IMC architectures that incorporates device, circuits, architecture, and interconnect under a single roof. The tool assesses the area, energy, and latency of the IMC accelerator. We analyze three interconnect cases to illustrate the versatility of the tool: (1) Point-to-point (P2P) and network-on-chip (NoC) based IMC architectures to demonstrate the criticality of the interconnect choice; (2) Area and energy optimization to improve IMC utilization and reduce on-chip interconnect cost; (3) Evaluation of a reconfigurable NoC to achieve minimum on-chip communication latency. Through these studies, we motivate the need for future work in the design of optimal on-chip and off-chip interconnect fabrics for IMC architectures.