Yang Zhao, Chen Liang, Luchen, Jianning Deng, Liangliang He
{"title":"基于55nm平台的20um划线线和集成测试PAD的经济布局解决方案","authors":"Yang Zhao, Chen Liang, Luchen, Jianning Deng, Liangliang He","doi":"10.1109/CSTIC52283.2021.9461527","DOIUrl":null,"url":null,"abstract":"In this work, an economic layout is designed for production of small sized chip with 20 um scribe line and integrated chip yield test pad. Three different kinds of layout are presented and thoroughly analyzed. Compared-with conventional 60 um scribe line layout, there is about 1 7% increase of chip quantity for a 20 um scribe line-layout with concentrated stacking mode of test key (TK) and marks. Such a novel layout maybe can be further expanded to different technology nodes and wafer size.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"2006 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Economic Layout Solution with 20 UM Scribe Line and Integrated Test PAD Based on 55 NM Platform\",\"authors\":\"Yang Zhao, Chen Liang, Luchen, Jianning Deng, Liangliang He\",\"doi\":\"10.1109/CSTIC52283.2021.9461527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, an economic layout is designed for production of small sized chip with 20 um scribe line and integrated chip yield test pad. Three different kinds of layout are presented and thoroughly analyzed. Compared-with conventional 60 um scribe line layout, there is about 1 7% increase of chip quantity for a 20 um scribe line-layout with concentrated stacking mode of test key (TK) and marks. Such a novel layout maybe can be further expanded to different technology nodes and wafer size.\",\"PeriodicalId\":186529,\"journal\":{\"name\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"2006 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC52283.2021.9461527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC52283.2021.9461527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Economic Layout Solution with 20 UM Scribe Line and Integrated Test PAD Based on 55 NM Platform
In this work, an economic layout is designed for production of small sized chip with 20 um scribe line and integrated chip yield test pad. Three different kinds of layout are presented and thoroughly analyzed. Compared-with conventional 60 um scribe line layout, there is about 1 7% increase of chip quantity for a 20 um scribe line-layout with concentrated stacking mode of test key (TK) and marks. Such a novel layout maybe can be further expanded to different technology nodes and wafer size.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
