An Economic Layout Solution with 20 UM Scribe Line and Integrated Test PAD Based on 55 NM Platform

Abstract

In this work, an economic layout is designed for production of small sized chip with 20 um scribe line and integrated chip yield test pad. Three different kinds of layout are presented and thoroughly analyzed. Compared-with conventional 60 um scribe line layout, there is about 1 7% increase of chip quantity for a 20 um scribe line-layout with concentrated stacking mode of test key (TK) and marks. Such a novel layout maybe can be further expanded to different technology nodes and wafer size.