{"title":"减少晶圆测试中探针卡接触电阻的复测研究","authors":"Hua Li, Deguang Zheng","doi":"10.1109/CSTIC52283.2021.9461487","DOIUrl":null,"url":null,"abstract":"To study the mechanism how to minimize the probe card contact resistance as to take least retest operation during wafer test. Calculate the retest rate with variant approaches to reduce the contact resistance between probe card needles and silicon wafer. A design of experiment (DOE) is used to find the most effective cleaning parameters and to spot the threshold of cleaning parameters set which is a balance for a good needle cleaning performance and reasonable probe card life. Deliver a formular to calculate retest rate with given cleaning parameters and locate the optimization values to achieve the lowest retest rate.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Study on Retest Reduction by Minimizing Probe Card Contact Resistance at Wafer Test\",\"authors\":\"Hua Li, Deguang Zheng\",\"doi\":\"10.1109/CSTIC52283.2021.9461487\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"To study the mechanism how to minimize the probe card contact resistance as to take least retest operation during wafer test. Calculate the retest rate with variant approaches to reduce the contact resistance between probe card needles and silicon wafer. A design of experiment (DOE) is used to find the most effective cleaning parameters and to spot the threshold of cleaning parameters set which is a balance for a good needle cleaning performance and reasonable probe card life. Deliver a formular to calculate retest rate with given cleaning parameters and locate the optimization values to achieve the lowest retest rate.\",\"PeriodicalId\":186529,\"journal\":{\"name\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 China Semiconductor Technology International Conference (CSTIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSTIC52283.2021.9461487\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC52283.2021.9461487","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Study on Retest Reduction by Minimizing Probe Card Contact Resistance at Wafer Test
To study the mechanism how to minimize the probe card contact resistance as to take least retest operation during wafer test. Calculate the retest rate with variant approaches to reduce the contact resistance between probe card needles and silicon wafer. A design of experiment (DOE) is used to find the most effective cleaning parameters and to spot the threshold of cleaning parameters set which is a balance for a good needle cleaning performance and reasonable probe card life. Deliver a formular to calculate retest rate with given cleaning parameters and locate the optimization values to achieve the lowest retest rate.