Exploring Gate-Cut Patterning Approaches Using Simulation and Defect Modelling

Abstract

Gate patterning is a critical step during CMOS transistor fabrication. As devices scale down in dimension, the gate-cut process has become increasingly important due to its significant impact on device performance and chip yield. Different gate-cut approaches have been developed for varying node integration requirements. In this paper, several gate-cut approaches are simulated using SEMulator3D®, a process and defect modeling platform. The simulation revealed both advantages and disadvantages to various gate-cut patterning approaches and provided guidance on improved process flow selection. Dummy gate-cut process window checks, along with poly line end residue modelling, have also been completed during this study and highlighted areas for potential process improvements and defect reduction.