Perry Li, R. Qiu, H. Zhou, J. Liu, K. Yang, C. Xu, E. Wu, L. Du, K. Lin, J. Feng, M. Chi
{"title":"Impact of Contact Misalignment on VT for Trench Power Mosfet","authors":"Perry Li, R. Qiu, H. Zhou, J. Liu, K. Yang, C. Xu, E. Wu, L. Du, K. Lin, J. Feng, M. Chi","doi":"10.1109/CSTIC52283.2021.9461420","DOIUrl":null,"url":null,"abstract":"Power ICs and devices, as key components for high performance systems with Artificial-Intelligence and Internet-of- Things (AI/loT), need to have superior quality and reliability with low Ron and good breakdown voltage. This paper briefly describes how the internal Vt's are impacted by the spacing from contact edge to the vertical channel. The trans-conductance of Id vs Vg is sensitive to detect the internal Vt's. The power MOS and IGBT with multiple Vt's can be formed by designing the contact layout with intentional varying the spacing to the vertical channel for digital info storage in new applications.","PeriodicalId":186529,"journal":{"name":"2021 China Semiconductor Technology International Conference (CSTIC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC52283.2021.9461420","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Power ICs and devices, as key components for high performance systems with Artificial-Intelligence and Internet-of- Things (AI/loT), need to have superior quality and reliability with low Ron and good breakdown voltage. This paper briefly describes how the internal Vt's are impacted by the spacing from contact edge to the vertical channel. The trans-conductance of Id vs Vg is sensitive to detect the internal Vt's. The power MOS and IGBT with multiple Vt's can be formed by designing the contact layout with intentional varying the spacing to the vertical channel for digital info storage in new applications.