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2013 Proceedings of the ESSCIRC (ESSCIRC)最新文献

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A 80µW 30fps 104 × 104 all-nMOS pixels CMOS imager with 7-bit PWM ADC for robust detection of relative intensity change 一个80µW 30fps 104 × 104全nmos像素CMOS成像仪，带有7位PWM ADC，用于鲁棒检测相对强度变化
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649133
Michele Benetti, M. Gottardi, Z. Smilansky
{"title":"A 80µW 30fps 104 × 104 all-nMOS pixels CMOS imager with 7-bit PWM ADC for robust detection of relative intensity change","authors":"Michele Benetti, M. Gottardi, Z. Smilansky","doi":"10.1109/ESSCIRC.2013.6649133","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649133","url":null,"abstract":"The presented vision sensor features low-power pixel-level programmable dynamic background subtraction as low-level image processing aimed at detecting unusual events occurring in the scene. Each pixel compares its current photogenerated signal with two threshold voltages, defining the boundary conditions outside which the signal is to be considered anomalous, if compared to its past history. In case of anomalous behavior, the pixel one-bit output will be asserted. The 17 transistors square pixel has a pitch of 16μm with a fill-factor of 21%. The 104 × 104 pixel sensor, fabricated in a 0.35 μm CMOS, has a power consumption of 80μW at 30 fps, when the sensor array is powered at 3.3V and the digital part at 1.5V. This turns into a pixel power consumption per frame of 246pW/pixel · frame.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114725122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators 用SRAM环形振荡器测量三维技术中硅通孔(tsv)对性能的影响
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649162
J. B. Kuang, K. Jenkins, K. Stawiasz, J. Schaub
{"title":"Performance impact of through-silicon vias (TSVs) in three-dimensional technology measured by SRAM ring oscillators","authors":"J. B. Kuang, K. Jenkins, K. Stawiasz, J. Schaub","doi":"10.1109/ESSCIRC.2013.6649162","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649162","url":null,"abstract":"A compact SRAM ring oscillator circuit for local, in-situ, probing of device performance is described. Applied to three-dimensional integrated circuit technology (3DI), the circuit is used to determine if there is any effect on SRAM performance when the cells are placed in close proximity to through-silicon vias (TSVs).","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126749687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An integrated ultracapacitor fast mains charger with combined power/current optimisation 集成的超级电容器快速电源充电器，结合功率/电流优化
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649097
R. Bodnar, W. Redman-White
{"title":"An integrated ultracapacitor fast mains charger with combined power/current optimisation","authors":"R. Bodnar, W. Redman-White","doi":"10.1109/ESSCIRC.2013.6649097","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649097","url":null,"abstract":"This paper presents a novel integrated self-oscillating step-down converter for the fast charging of stacks of large ultracapacitors from a 230V AC mains source. The charger architecture controls both power and current to optimise the charge rate with respect to the limitations imposed by the mains source and the capacitors themselves. The circuit has been fabricated in a 0.35μm bulk medium voltage CMOS, process.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124847722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 4 a peak current and 2 ns pulse width CMOS laser diode driver for high measurement rate applications 一个4 A峰值电流和2 ns脉冲宽度CMOS激光二极管驱动器用于高测量速率的应用
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649146
J. Nissinen, J. Kostamovaara
{"title":"A 4 a peak current and 2 ns pulse width CMOS laser diode driver for high measurement rate applications","authors":"J. Nissinen, J. Kostamovaara","doi":"10.1109/ESSCIRC.2013.6649146","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649146","url":null,"abstract":"A single chip integrated laser diode driver has been designed and fabricated in a high-voltage 0.35μm 50V CMOS technology for pulsed time-of-flight (TOF) laser ranging applications. A peak current and pulse width of approximately 4 A and 2ns, respectively, can be achieved through a low ohmic load in a driver structure with four parallel switching devices. With a commercial pulsed laser diode a peak optical power of 2.3 W with a pulse width of 1.5 ns was measured. Measurements showed also that a pulsing rate of at least 1 MHz is achievable. With this pulse rate the current consumption from 5.5 V and 50 V supplies is 9 mA and 5 mA, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"499 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC 基于32nm GALS MPSoC的细粒度变化感知动态vdd跳频AVFS架构
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649071
E. Beigné, I. Miro-Panadès, Y. Thonnart, L. Alacoque, P. Vivet, S. Lesecq, D. Puschini, F. Thabet, Benoît Tain, K. Benchehida, S. Engels, Robin Wilson, D. Fuin
{"title":"A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC","authors":"E. Beigné, I. Miro-Panadès, Y. Thonnart, L. Alacoque, P. Vivet, S. Lesecq, D. Puschini, F. Thabet, Benoît Tain, K. Benchehida, S. Engels, Robin Wilson, D. Fuin","doi":"10.1109/ESSCIRC.2013.6649071","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649071","url":null,"abstract":"In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to a worst case approach, our proposal also allows a frequency boosting around 25% for a total area overhead of 10% including local frequency/voltage actuators, sensors and digital controller.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS 一种40MHz-BW两步开环vco型ADC，采用42fJ/步FoM，采用40nm CMOS
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649139
Xinpeng Xing, Peng Gao, G. Gielen
{"title":"A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS","authors":"Xinpeng Xing, Peng Gao, G. Gielen","doi":"10.1109/ESSCIRC.2013.6649139","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649139","url":null,"abstract":"A two-step open-loop VCO-based ADC with 1st-order noise shaping and intrinsic nonlinearity mitigation is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high efficiency is achieved. The nonlinearities of the VCOs in the coarse and fine quantizers are improved by a distortion cancellation and a voltage swing reduction scheme respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7dB SFDR. The power consumption is only 2.57mW, corresponding to an excellent FoM of 42fJ/step.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131234961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A resistor-based temperature sensor for MEMS frequency references 基于电阻的MEMS频率参考温度传感器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649113
M. Shahmohammadi, Kianoush Souri, K. Makinwa
{"title":"A resistor-based temperature sensor for MEMS frequency references","authors":"M. Shahmohammadi, Kianoush Souri, K. Makinwa","doi":"10.1109/ESSCIRC.2013.6649113","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649113","url":null,"abstract":"This paper presents a CMOS temperature sensor intended for the temperature compensation of MEMS frequency references. It is based on a Wien bridge RC filter, whose phase-shift, due to the temperature dependency of the resistors used, is temperature dependent. This phase shift is then digitized by a phase domain sigma-delta modulator. The sensor was implemented in 0.18μm CMOS, consumes 36 μW and achieves 6mK resolution in a conversion time of 100msec. After batch calibration and a 3-point trim, it achieves ±0.15°C (3σ) inaccuracy over the industrial range (-40°C to 85°C).","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
2×(4×)128 time-gated CMOS single photon avalanche diode line detector with 100 ps resolution for Raman spectroscopy 2×(4×)128时间门控CMOS单光子雪崩二极管线探测器，分辨率为100ps，用于拉曼光谱
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649130
I. Nissinen, Antti-Kalle Länsman, J. Nissinen, Jouni Holma, J. Kostamovaara
{"title":"2×(4×)128 time-gated CMOS single photon avalanche diode line detector with 100 ps resolution for Raman spectroscopy","authors":"I. Nissinen, Antti-Kalle Länsman, J. Nissinen, Jouni Holma, J. Kostamovaara","doi":"10.1109/ESSCIRC.2013.6649130","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649130","url":null,"abstract":"A 2×(4×)128 multiphase time-gated single photon avalanche diode (SPAD) line detector has been designed and fabricated in a high voltage 0.35 μm CMOS technology for Raman spectroscopy. The time positions of the photons can be measured with the resolution of 100 ps using four time gates over the whole line detector simultaneously. This approach enables to reduce the fluorescence background of the Raman spectrum markedly. Measurements showed that the time gates can be distributed over the whole line detector with the accuracy of ± 35 ps which is adequate for a time-gated pulsed Raman spectroscopy using a laser pulse width of approximately 150 ps.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"550 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116234784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links 1 v 1.25 gbps CMOS模拟前端，用于短距离光链路
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649142
C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, C. Aldea, S. Celma
{"title":"A 1-V 1.25-Gbps CMOS analog front-end for short reach optical links","authors":"C. Gimeno, C. Sánchez-Azqueta, E. Guerrero, C. Aldea, S. Celma","doi":"10.1109/ESSCIRC.2013.6649142","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649142","url":null,"abstract":"This paper presents a new adaptive equalizer for short reach applications through low-cost plastic optical fiber. The adaptive equalizer uses the spectrum balancing technique to compensate the limited bandwidth caused by the fiber and the external photodiode. The prototype has been implemented in a standard 0.18-μm CMOS process fed at 1 V. It consumes 38.6 mW at 1.25 Gb/s.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122122798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS 无电源序列400Mbps 90µW 6000µm2 1.8V-3.3V耐应力I/O缓冲器，28nm CMOS
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649066
Vinod Kumar, Mohd. Rizvi
{"title":"Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS","authors":"Vinod Kumar, Mohd. Rizvi","doi":"10.1109/ESSCIRC.2013.6649066","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649066","url":null,"abstract":"A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"735 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123860308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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