Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS

Abstract

A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.