A 40MHz-BW two-step open-loop VCO-based ADC with 42fJ/step FoM in 40nm CMOS

Abstract

A two-step open-loop VCO-based ADC with 1st-order noise shaping and intrinsic nonlinearity mitigation is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high efficiency is achieved. The nonlinearities of the VCOs in the coarse and fine quantizers are improved by a distortion cancellation and a voltage swing reduction scheme respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The design is implemented in 40nm CMOS and shows that, with 1.6GHz sampling frequency, the two-step VCO-based ADC reaches 40MHz bandwidth, 59.5dB SNDR and 67.7dB SFDR. The power consumption is only 2.57mW, corresponding to an excellent FoM of 42fJ/step.