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2013 Proceedings of the ESSCIRC (ESSCIRC)最新文献

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Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control 基于后门偏置控制的28nm UTBB FD-SOI技术4T、6T、8T、10T SRAM位单元电路优化
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649161
V. Asthana, Malathi Kar, J. Jimenez, J. Noel, S. Haendler, P. Galy
{"title":"Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control","authors":"V. Asthana, Malathi Kar, J. Jimenez, J. Noel, S. Haendler, P. Galy","doi":"10.1109/ESSCIRC.2013.6649161","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649161","url":null,"abstract":"SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. The back-gate terminal biasing leads to forward or reverse bias of the transistors and has been used to improve the bitcell electrical metrics. The derived 6T bitcell variants show a gain of 67% (25%) in cell current at 0.6V (1V), 45% reduction in write time at 0.6V, along with a gain in either write margin or static noise margin. Two 4T load-less bitcell variants using back-gate bias have been fabricated and compared for performance, power and stability margins. The back-gate biasing concept has been extended to optimize 8T, 10T bitcells and their simulation results are also presented.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122769378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A plastic waveguide receiver in 40nm CMOS with on-chip bondwire antenna 采用片上键合线天线的40nm CMOS塑料波导接收器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649141
M. Tytgat, P. Reynaert
{"title":"A plastic waveguide receiver in 40nm CMOS with on-chip bondwire antenna","authors":"M. Tytgat, P. Reynaert","doi":"10.1109/ESSCIRC.2013.6649141","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649141","url":null,"abstract":"This paper presents the design and measurements of a 40 nm CMOS BPSK and multilevel ASK receiver for wired connections through a plastic waveguide, operating at 87 GHz. In a measurement setup containing the receiver chip with bondwire dipole antenna and a long piece of polypropylene waveguide with a rectangular cross-section of 2.2 mm by 0.9 mm, a maximum datarate of 9 Gbit/s over a distance of 60 cm and 2.5 Gbit/s over a distance of 9 m is measured, both with a bit error rate of less than 10-12 and a PRBS length of 27 - 1. The chip consumes 50 mW of DC power from a 0.9 V supply. The total chip area is 2.1 mm2, of which 52 % is occupied by the antenna and reflector.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128086812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS 3.4mW 2.3- 2.7 ghz频率合成器，0.18µm CMOS
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649070
C. Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, N. Cheng
{"title":"A 3.4mW 2.3-to-2.7GHz frequency synthesizer in 0.18-µm CMOS","authors":"C. Chang, Ching-Yuan Yang, Yu Lee, Jun-Hong Weng, N. Cheng","doi":"10.1109/ESSCIRC.2013.6649070","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649070","url":null,"abstract":"Constructed from a current reused architecture for low power consumption, a cascode topology of an LC VCO and a divide-by-4 prescaler is used in a PLL. In the prescaler, the first-stage divide-by-2 divider is an injection locking circuit used to frequency lock to an incident signal to perform frequency division. The next-stage divide-by-2 divider uses the conventional D-type filpflop with optimizing the threshold voltage to lower the operating voltage. Implemented with 1.8-V 0.18-μm CMOS, the PLL provides the phase noise of -121.67 dBc/Hz at 1-MHz offset and consumes 3.4 mW at 2.4 GHz.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120922362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
60-GHz, 9-µW wake-up receiver for short-range wireless communications 60ghz, 9µW唤醒接收器，用于短距离无线通信
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649153
Toshiki Wada, M. Ikebe, E. Sano
{"title":"60-GHz, 9-µW wake-up receiver for short-range wireless communications","authors":"Toshiki Wada, M. Ikebe, E. Sano","doi":"10.1109/ESSCIRC.2013.6649153","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649153","url":null,"abstract":"We present an ultra-low power 60-GHz band wake-up receiver (WuRx) designed and fabricated with a 0.18-μm RF CMOS low-cost technology. The WuRx consists of an envelope detector, high-gain baseband amplifier, and clock and data recovery (CDR) circuit. Subthreshold-operated offset-voltage cancellers are used in the detector and baseband amplifier. The envelope detector can operate for an on-off keying (OOK) signal with a low bit-rate baseband and 60-GHz carrier, which is higher than the cutoff frequency (fT) of 0.18-μm MOSFETs. This is because the fT defines the maximum operating bit-rate of the baseband signal. The CDR circuit is composed of a clock recovery circuit using an injection-locked oscillator, short pulse generator, and D-type flip/flop. The fabricated WuRx successfully operates with power consumption of only 9 μW from a 1.5-V supply and a high sensitivity of -68 dBm for a 350-kbit/s OOK signal with a 60-GHz carrier. The CMOS die area is 1.09 mm2. This is the first successful fabrication of a 60-GHz WuRx.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Speed considerations for LDPD based time-of-flight CMOS 3D image sensors 基于LDPD的飞行时间CMOS 3D图像传感器的速度考虑
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649132
A. Süss, Christian Nitta, Andreas Spickermann, D. Durini, G. Varga, M. Jung, W. Brockherde, B. Hosticka, H. Vogt, S. Schwope
{"title":"Speed considerations for LDPD based time-of-flight CMOS 3D image sensors","authors":"A. Süss, Christian Nitta, Andreas Spickermann, D. Durini, G. Varga, M. Jung, W. Brockherde, B. Hosticka, H. Vogt, S. Schwope","doi":"10.1109/ESSCIRC.2013.6649132","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649132","url":null,"abstract":"Recently a 128×96 pixel range imager with a pitch of 40 μm and a fill factor of 38 % was presented for 3D range imaging measurements based on the pulse modulated (PM) time-of-flight (ToF) principle. This sensor employs a high-speed photodetector called lateral drift-field photodiode (LDPD). During the characterization insufficiencies in charge transfer were observed for low-light illumination. Here, characterization and analysis of the former imager is given and a redesign that circumvents the parasitic effects is demonstrated and verified by measurements on chip and on camera level.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114994255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Cyborg insects, neural dust and other things: Building interfaces between the synthetic and the multicellular 半机械昆虫，神经尘埃和其他东西:在合成细胞和多细胞之间建立接口
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-09-01 DOI: 10.1109/ESSDERC.2013.6818810
T. Blanche, J. Kleef, P. Ledochowitsch, T. L. Massey, R. Muller, D. Seo, M. Maharbiz
{"title":"Cyborg insects, neural dust and other things: Building interfaces between the synthetic and the multicellular","authors":"T. Blanche, J. Kleef, P. Ledochowitsch, T. L. Massey, R. Muller, D. Seo, M. Maharbiz","doi":"10.1109/ESSDERC.2013.6818810","DOIUrl":"https://doi.org/10.1109/ESSDERC.2013.6818810","url":null,"abstract":"As the computation and communication circuits we build radically miniaturize (i.e. become so low power that 1 pJ is sufficient to bang out a bit of information over a wireless transceiver; become so small that 500 μm2 of thinned CMOS can hold a reasonable sensor front-end and digital engine), the barrier to introducing all sorts of interfaces and control loops into organisms will lower radically. Put another way, the rapid pace of computation and communication miniaturization is swiftly blurring the line between the technological base that created us and the technological based we've created. This talk will provide an overview of recent work in the Maharbiz lab that touches on this concern. Some of this will cover our ongoing exploration of the remote control of insects in free flight via implantable radio-equipped miniature neural stimulating systems and more recent work in next generation mammalian neural interfaces for brain machine interface (BMI) applications, including neural dust.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128002221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array 用于高密度ECoG柔性有源电极阵列的85 dB动态范围1.2 mW 156 kS/s生物电位记录IC
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-09-01 DOI: 10.1109/ESSCIRC.2013.6649092
S. Ha, Jongkil Park, Y. Chi, J. Viventi, J. Rogers, G. Cauwenberghs
{"title":"85 dB dynamic range 1.2 mW 156 kS/s biopotential recording IC for high-density ECoG flexible active electrode array","authors":"S. Ha, Jongkil Park, Y. Chi, J. Viventi, J. Rogers, G. Cauwenberghs","doi":"10.1109/ESSCIRC.2013.6649092","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649092","url":null,"abstract":"We present the design, implementation, and experimental characterization of a low-noise low-power biopotential recording integrated circuit (IC) in support of a fully implantable, high-density, actively multiplexed and flexible 32×32 electrode array for electrocorticography (ECoG) neural recording. Each ECoG recording IC contains an 8-channel ADC, each serving one column and multiplexing up to 32 rows in the external ECoG array. Each column ADC converts signal coarsely by 10-bit successive approximation (SA), and performs fine conversion of the residue by 7-bit 1st order incremental delta-sigma (ΔΣ) conversion. One bit of overlap between SA and ΔΣ stages supports wide dynamic range with an instantaneous core range of 3.9 mV, sufficiently larger than typical ECoG signals, while handling electrochemical and process variations in the ECoG electrode array up to ±1 V. Tests show a measured dynamic range of 85 dB and CMRR of 87 dB at 19.5 kS/s and at 19.4 μA from 3.3 V per ADC channel. The 8-channel IC occupies 18 mm2 in 0.6 μm 2P3M CMOS.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131295629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators 高速，高精度分数- n频率合成器使用嵌套混合基数数字Δ-Σ调制器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-09-01 DOI: 10.1109/ESSCIRC.2013.6649118
Michael Peter Kennedy, B. Fitzgibbon, A. Harney, H. Shanan, M. Keaveney
{"title":"High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators","authors":"Michael Peter Kennedy, B. Fitzgibbon, A. Harney, H. Shanan, M. Keaveney","doi":"10.1109/ESSCIRC.2013.6649118","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649118","url":null,"abstract":"If the modulus of the DΔΣM in a fractional-N frequency synthesizer is a power of two, then the output frequency is constrained to be a rational multiple of the phase detector frequency (fPD), where the denominator of the rational multiplier is a power of two. If the required output frequency is not related to fPD in this way, one is forced to approximate the ratio by using a small programmable modulus DΔΣM or a very large power of two modulus. Both solutions involve additional hardware. In addition, the programmable modulus solution can suffer from spurs, while the large power of two lacks accuracy. This paper presents a new solution, based on mixed-radix algebra, where the required ratio is formed by combining two different moduli. The programmable modulus solves the accuracy problem, while the large power of two modulus minimizes the spur content. In addition, the phase detector can be clocked at high speed.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132888459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction 一种基于注入锁定的可编程分数分频器，具有0.2分频步长，用于量化降噪
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-09-01 DOI: 10.1109/ESSCIRC.2013.6649115
R. Thirunarayanan, D. Ruffieux, C. Enz
{"title":"An injection-locking based programmable fractional frequency divider with 0.2 division step for quantization noise reduction","authors":"R. Thirunarayanan, D. Ruffieux, C. Enz","doi":"10.1109/ESSCIRC.2013.6649115","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649115","url":null,"abstract":"A programmable fractional frequency divider with a division step size of 0.2 has been proposed in this paper. The circuit consists of a 5-stage ring oscillator which is injection locked to an external source. The different phases from the ring oscillator are linearly combined in a Phase Combiner (PC) based on the select signals produced by a state machine. These select signals are resynchronized with the phases to avoid glitches. This phase combined signal is then presented to a low-power dynamic divider set to division by an integer I. The result is a division by I.F where F is a multiple of the division step size 0.2. When used in a fractional-N PLL, this division step size reduction has the effect of reducing the quantization noise by 14 dB as compared to the case where a conventional multi-modulus divider (MMD) with division ratio step size of 1 is used.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121861009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Cross-layer optimization of QRD accelerators QRD加速器的跨层优化
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-09-01 DOI: 10.1109/ESSCIRC.2013.6649123
U. Vishnoi, T. Noll
{"title":"Cross-layer optimization of QRD accelerators","authors":"U. Vishnoi, T. Noll","doi":"10.1109/ESSCIRC.2013.6649123","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649123","url":null,"abstract":"QR decomposition accelerators are attractive SoC components for many applications. A new linear QRD array is proposed based on the Givens-algorithm and CORDIC (Coordinate Rotate Digital Computer) rotations. In order to achieve high area- and energy-efficiency a systematic design space exploration has to be applied. Thereby the strong interactions between the architecture, micro-architecture and circuit level have to be considered. Based on architecture templates and pre-characterization of basic building blocks an algebraic cost-model is presented allowing for a cross-layer design space exploration with adequate accuracy in reasonable time. As a result from this quantitative optimization approach, a 16×16-QRD macro performing 30 million QRDs per second on 0.3 mm2 area and 160 pJ per QRD is derived.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114811920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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