Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Abstract

SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. The back-gate terminal biasing leads to forward or reverse bias of the transistors and has been used to improve the bitcell electrical metrics. The derived 6T bitcell variants show a gain of 67% (25%) in cell current at 0.6V (1V), 45% reduction in write time at 0.6V, along with a gain in either write margin or static noise margin. Two 4T load-less bitcell variants using back-gate bias have been fabricated and compared for performance, power and stability margins. The back-gate biasing concept has been extended to optimize 8T, 10T bitcells and their simulation results are also presented.