{"title":"Cross-layer optimization of QRD accelerators","authors":"U. Vishnoi, T. Noll","doi":"10.1109/ESSCIRC.2013.6649123","DOIUrl":null,"url":null,"abstract":"QR decomposition accelerators are attractive SoC components for many applications. A new linear QRD array is proposed based on the Givens-algorithm and CORDIC (Coordinate Rotate Digital Computer) rotations. In order to achieve high area- and energy-efficiency a systematic design space exploration has to be applied. Thereby the strong interactions between the architecture, micro-architecture and circuit level have to be considered. Based on architecture templates and pre-characterization of basic building blocks an algebraic cost-model is presented allowing for a cross-layer design space exploration with adequate accuracy in reasonable time. As a result from this quantitative optimization approach, a 16×16-QRD macro performing 30 million QRDs per second on 0.3 mm2 area and 160 pJ per QRD is derived.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649123","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
QR decomposition accelerators are attractive SoC components for many applications. A new linear QRD array is proposed based on the Givens-algorithm and CORDIC (Coordinate Rotate Digital Computer) rotations. In order to achieve high area- and energy-efficiency a systematic design space exploration has to be applied. Thereby the strong interactions between the architecture, micro-architecture and circuit level have to be considered. Based on architecture templates and pre-characterization of basic building blocks an algebraic cost-model is presented allowing for a cross-layer design space exploration with adequate accuracy in reasonable time. As a result from this quantitative optimization approach, a 16×16-QRD macro performing 30 million QRDs per second on 0.3 mm2 area and 160 pJ per QRD is derived.