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A dual vertical Hall latch with direction detection 具有方向检测的双垂直霍尔门闩
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649110
Dan Stoica, M. Motz
{"title":"A dual vertical Hall latch with direction detection","authors":"Dan Stoica, M. Motz","doi":"10.1109/ESSCIRC.2013.6649110","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649110","url":null,"abstract":"A chopped vertical Hall sensor for detecting the speed and motion direction of magnetic encoder wheels is presented. It achieves low offset and low noise even in the case of the low intrinsic sensitivity and high voltage dependency of offset common to the vertical Hall devices. It features a combination of spinning and stacking techniques together with mixed sampled and continuous time processing, capable of reaching 36μT switching noise at 25°C and typical 0.25mT offset in a temperature range from -40 °C to 150 °C. Additionally, it employs sensitivity compensation of mechanical stress for reducing packaging influences on the sensor. This allows switching point measurement at wafer level, based on injecting current in an integrated wire on chip.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
FinFETs - Technology and circuit design challenges finfet -技术和电路设计挑战
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649058
W. Maszara, M. Lin
{"title":"FinFETs - Technology and circuit design challenges","authors":"W. Maszara, M. Lin","doi":"10.1109/ESSCIRC.2013.6649058","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649058","url":null,"abstract":"It took quarter of a century for multi-gate transistor to make it from first demonstration in research to a product - 22nm technology node microprocessor in 2012. FinFETs offer superior performance over incumbent planar devices due to their significantly improved electrostatics. FinFET technology faced two key barriers to their implementation in products: demanding process integration and its significant impact on layout and circuit design methodology. In this paper we focus on challenges and tradeoffs in both of these areas. Fin shape, pitch, isolation, doping, crystallographic orientation and stressing as well as device parasitics, performance and patterning approaches will be discussed. Implementation of high mobility materials for finFET devices will also be briefly reviewed as well as design challenges for logic and SRAM circuits.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"73 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127389485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump 集成电荷泵的40nm, 454MHz 114 fJ/bit面积高效SRAM存储器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649107
B. Rooseleer, W. Dehaene
{"title":"A 40 nm, 454MHz 114 fJ/bit area-efficient SRAM memory with integrated charge pump","authors":"B. Rooseleer, W. Dehaene","doi":"10.1109/ESSCIRC.2013.6649107","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649107","url":null,"abstract":"In this paper, a 256 kbit high speed, ultra-low power SRAM is presented. It runs at a speed of 454MHz with a power of only 29 pJ/access or 114 fJ/access/bit. Retention mode leakage is only 86 μW. Combining three novel techniques with proven methods assures a design which can cope with the challenges introduced by deep submicron technologies. The first technique, an integrated charge pump, enables low swing signals to be used to save active energy while only one external supply is required. A second novelty is the use of a low swing scheme for both read and write. This results in simplified local periphery which reduces area overhead to a very low 4 %. Last, segmented horizontal control lines ensure correct operation in the presence of large RC-delays on long metal lines. The design was fabricated in a 40nm low standby power technology. Measurements prove the functionality of the proposed techniques.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126405713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS 双vt 4kb子vt存储器，在65nm CMOS中泄漏小于1 pW/bit
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649106
O. Andersson, B. Mohammadi, P. Meinerzhagen, A. Burg, J. Rodrigues
{"title":"Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS","authors":"O. Andersson, B. Mohammadi, P. Meinerzhagen, A. Burg, J. Rodrigues","doi":"10.1109/ESSCIRC.2013.6649106","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649106","url":null,"abstract":"Two standard-cell based subthreshold (sub-VT) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-VT approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4× and 8× compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7× and 2× to 39 and 29 fJ, respectively.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128092407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Oxide electronics for imaging and displays 成像和显示用氧化物电子器件
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649120
A. Nathan, Sungsik Lee, S. Jeon
{"title":"Oxide electronics for imaging and displays","authors":"A. Nathan, Sungsik Lee, S. Jeon","doi":"10.1109/ESSCIRC.2013.6649120","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649120","url":null,"abstract":"Despite material weaknesses, considerable progress has been made in designing large area systems such as displays and imaging arrays. This talk will address the various large area technologies, and in particular, review amorphous oxide semiconductors and associated design approaches, along with driving schemes for displays, imaging and other applications.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132950284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual-band RF receiver for GPS and compass systems in 55-nm CMOS 55纳米CMOS双波段射频接收机，用于GPS和指南针系统
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649100
Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Jianfei Wu, Dun Yan, Z. Zhuang
{"title":"Dual-band RF receiver for GPS and compass systems in 55-nm CMOS","authors":"Songting Li, Jiancheng Li, Xiaochen Gu, Hongyi Wang, Jianfei Wu, Dun Yan, Z. Zhuang","doi":"10.1109/ESSCIRC.2013.6649100","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649100","url":null,"abstract":"A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L1 and Compass-B1 in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive the dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoid any LO crosstalk. A digital automatic gain control (AGC) loop is utilized to improve the receiver's robustness by optimizing the conversion gain of the analog-to-digital converter (ADC). While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure (NF) of about 1.8 dB, an image rejection (IMR) of more than 35 dB, a maximum voltage gain of about 110 dB, a gain dynamic range of more than 68 dB, and an input-referred 1 dB compression point (P1dB) of about -36.5 dBm with an active die area of 1.5 ×1.4 mm2 for the whole chip.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131990863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A DC-connectable multi-channel biomedical data acquisition ASIC with mains frequency cancellation 一种可直流连接的多通道生物医学数据采集专用集成电路
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649094
Philipp Schönle, Felix Schulthess, S. Fateh, Roger Ulrich, Fiona Huang, T. Burger, Qiuting Huang
{"title":"A DC-connectable multi-channel biomedical data acquisition ASIC with mains frequency cancellation","authors":"Philipp Schönle, Felix Schulthess, S. Fateh, Roger Ulrich, Fiona Huang, T. Burger, Qiuting Huang","doi":"10.1109/ESSCIRC.2013.6649094","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649094","url":null,"abstract":"This paper presents an 8-channel biomedical data acquisition ASIC achieving 108dB of dynamic range (DR). Each channel includes a 13bit DAC to compensate differential input offset of up to ±300mV, preventing saturation of the high-gain instrumentation amplifier. Chopper stabilization and DAC-noise low-pass filtering lead to an input-referred noise of 0.8μVRMS. Data processing algorithms, implemented on an FPGA, are employed to remove artefacts due to sudden DAC-switching and to cancel 50/60Hz mains interference including its harmonics. The chip is fabricated in 130nm CMOS, occupying an active area of 2.2mm2 and consuming 15mW from 1.2V and 3.3V supplies.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"215 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134542326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Embedded fully self-biased switched-capacitor for energy and area-efficient cholesteric LCD drivers 嵌入式完全自偏置开关电容器的能源和面积高效胆甾液晶驱动器
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649145
W. Chou, Po-Hsien Huang, Ming-Yan Fan, Ke-Horng Chen, K. Wen, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Jui-Lung Chen
{"title":"Embedded fully self-biased switched-capacitor for energy and area-efficient cholesteric LCD drivers","authors":"W. Chou, Po-Hsien Huang, Ming-Yan Fan, Ke-Horng Chen, K. Wen, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Jui-Lung Chen","doi":"10.1109/ESSCIRC.2013.6649145","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649145","url":null,"abstract":"The embedded fully self-biased switched-capacitor (FSBSC) with single-inductor high voltage bipolar-output (SIHBO) converter is proposed to achieve the energy and area-efficient driving scheme for the paper-like cholesteric liquid crystal display (Ch-LCD), which becomes the next generation of electronic readers in the consumer markets. As the compact power management module, SIHBO converter can provide +/-35V bipolar outputs for row driving. Besides, the embedded FSBSC is utilized to generate the different voltage levels for modulating the gray-color in column driving scheme. This combination carries out the effective driving operation for Ch-LCD through the demand of timing control unit. Experimental results show the achievement of +/-35V output voltage in the SIHBO converter and the variety voltage levels generated from FSBSC. The peak efficiency is up to 84% with the silicon area of 6.53 mm2.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals 采用并行采样结构的11b 1GS/s ADC，可提高多载波信号的SNDR
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649087
Y. Lin, K. Doris, E. Janssen, A. Zanikopoulos, A. Murroni, G. V. D. Weide, H. Hegt, A. Roermund
{"title":"An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals","authors":"Y. Lin, K. Doris, E. Janssen, A. Zanikopoulos, A. Murroni, G. V. D. Weide, H. Hegt, A. Roermund","doi":"10.1109/ESSCIRC.2013.6649087","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649087","url":null,"abstract":"This paper presents an 11b 1GS/s ADC with a parallel sampling architecture to enhance SNDR for broadband multi-carrier signals. It contains two 1GS/s 11b sub-ADCs each achieving > 54dB SNDR for input frequencies up to Nyquist frequency and state-of-the-art linearity performance. The SNDR of the ADC with the parallel sampling architecture is improved by 5dB compared to its sub-ADCs when digitizing multi-carrier signals with large crest factors. This improvement is achieved at less than half the cost in power and area compared to the conventional approach. The chip is implemented in 65nm LP CMOS and consumes in total 350mW at 1GS/s.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115455366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression 9MHz滤波ADC，附加二阶ΔΣ调制器噪声抑制
2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI: 10.1109/ESSCIRC.2013.6649138
Mattias Andersson, Martin Anderson, Lars Sundström, S. Mattisson, P. Andreani
{"title":"A 9MHz filtering ADC with additional 2nd-order ΔΣ modulator noise suppression","authors":"Mattias Andersson, Martin Anderson, Lars Sundström, S. Mattisson, P. Andreani","doi":"10.1109/ESSCIRC.2013.6649138","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2013.6649138","url":null,"abstract":"This paper presents a filtering ADC for the LTE standard, where a Delta-Sigma modulator (DSM) is merged into the channel-select filter (CSF) of the LTE radio receiver. The CSF introduces an additional 2nd-order suppression of both quantization and thermal DSM noise, while the CSF transfer function is essentially maintained. The 65 nm CMOS prototype is clocked at 288MHz with a 9MHz LTE bandwidth, and has an input-referred noise of 8.1 nV/√Hz, 12 dB gain, and an in/out-of-band IIP3 of 11.5/27 dBVrms, with a power consumption of 11.3mW, resulting in state-of-the-art figure-of-merits (FOMs) for filtering ADCs.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115650487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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