Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS

Abstract

Two standard-cell based subthreshold (sub-VT) memories (SCMs) are presented. The SCMs accomplish the task of robust sub-VT storage and fill the gap of missing sub-VT memory compilers. The storage elements (latches) of these SCMs are custom-designed cells using a dual-VT approach to improve reliability and balance timing. Additionally, two read-logic styles are presented: 1) a segmented 3-state implementation that increases performance compared to a pure 3-state implementation; and 2) a purely MUX-based implementation with the first stage (NAND gate) integrated into the storage cell. Silicon measurements of two 4kb SCMs manufactured in a low-power 65nm CMOS technology show that read access speed increases by 4× and 8× compared to a pure 3-state implementation for the segmented 3-state and integrated NAND, respectively, while bit-access energy only increases by 2.7× and 2× to 39 and 29 fJ, respectively.