A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC

2013 Proceedings of the ESSCIRC (ESSCIRC) Pub Date : 2013-10-31 DOI:10.1109/ESSCIRC.2013.6649071

E. Beigné, I. Miro-Panadès, Y. Thonnart, L. Alacoque, P. Vivet, S. Lesecq, D. Puschini, F. Thabet, Benoît Tain, K. Benchehida, S. Engels, Robin Wilson, D. Fuin

引用次数: 23

Abstract

In order to optimize global energy efficiency in the context of dynamic Process-Voltage-Temperature variations in advanced nodes, a fine-grain Adaptive Voltage and Frequency Scaling architecture is proposed and implemented on a 32 nm GALS Multi-Processor SoC. Each Processing Element is an independent Voltage-Frequency island and shows up to 18.2% energy gains due to local adaptability. Compared to a worst case approach, our proposal also allows a frequency boosting around 25% for a total area overhead of 10% including local frequency/voltage actuators, sensors and digital controller.

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基于32nm GALS MPSoC的细粒度变化感知动态vdd跳频AVFS架构

为了在高级节点动态过程电压温度变化的背景下优化全局能源效率，提出了一种细粒度自适应电压和频率缩放架构，并在32nm GALS多处理器SoC上实现。每个处理单元是一个独立的电压频率岛，由于局部适应性，显示高达18.2%的能量增益。与最坏情况下的方法相比，我们的建议还允许频率提升约25%，总面积开销为10%，包括本地频率/电压执行器，传感器和数字控制器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2013 Proceedings of the ESSCIRC (ESSCIRC)

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