{"title":"无电源序列400Mbps 90µW 6000µm2 1.8V-3.3V耐应力I/O缓冲器，28nm CMOS","authors":"Vinod Kumar, Mohd. Rizvi","doi":"10.1109/ESSCIRC.2013.6649066","DOIUrl":null,"url":null,"abstract":"A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"735 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS\",\"authors\":\"Vinod Kumar, Mohd. Rizvi\",\"doi\":\"10.1109/ESSCIRC.2013.6649066\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.\",\"PeriodicalId\":183620,\"journal\":{\"name\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"volume\":\"735 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Proceedings of the ESSCIRC (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2013.6649066\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649066","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Power sequence free 400Mbps 90µW 6000µm2 1.8V–3.3V stress tolerant I/O buffer in 28nm CMOS
A power sequence independent I/O (Input/Output) buffer architecture for high voltage (up to 3.6V) application by using low voltage (1.8V) devices is proposed. In this a power sequence free, area and power efficient CRVG (Configurable Reference Voltage Generator) generates the internal reference voltage for the stacked devices to protect them from voltage stress. The proposed I/O buffer is designed in 28nm CMOS process by using standard 32Å gate-oxide devices. The silicon results confirmed up to 200 MHz successful operation in multiple (1.8V, 2.5V, 3.0V, 3.3V) supply range.
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