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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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A sequential redundant fault identification scheme and its application to test generation 一种序列冗余故障识别方法及其在测试生成中的应用
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367253
Hsing-Chung Liang, Chung-Len Lee, J. Chen
{"title":"A sequential redundant fault identification scheme and its application to test generation","authors":"Hsing-Chung Liang, Chung-Len Lee, J. Chen","doi":"10.1109/ATS.1994.367253","DOIUrl":"https://doi.org/10.1109/ATS.1994.367253","url":null,"abstract":"This work presents an efficient method to identify sequential redundant faults. The method is based on a simple procedure to identify the flip-flops which cannot be initialized and the circuit lines which cannot be controlled to definite values. The redundant faults are classified into four types and the method can identify each type of them. The method has been experimentally incorporated","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115787339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Netlist automatic extractor: "An image processing based software for bare board test data generation" 网表自动提取器:基于图像处理的裸板测试数据生成软件
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367227
A. Benali, L. Balme, C. Vaucher
{"title":"Netlist automatic extractor: \"An image processing based software for bare board test data generation\"","authors":"A. Benali, L. Balme, C. Vaucher","doi":"10.1109/ATS.1994.367227","DOIUrl":"https://doi.org/10.1109/ATS.1994.367227","url":null,"abstract":"Bare PCB (printed circuit board) test data generation softwares are based on vectorized calculations. When they fail, the automatic network list extractor software developed by IMD/TIMA succeeds thanks to image processing and pattern recognition on bitmaps.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"327 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114704395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fault detection by transient transition count testing 通过暂态跃迁计数检测故障
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367260
Kuo-Chan Huang, M. Chen, Chung-Len Lee, J. Chen
{"title":"Fault detection by transient transition count testing","authors":"Kuo-Chan Huang, M. Chen, Chung-Len Lee, J. Chen","doi":"10.1109/ATS.1994.367260","DOIUrl":"https://doi.org/10.1109/ATS.1994.367260","url":null,"abstract":"A new testing scheme, transient transition count (TTC) testing, which is able to detect hard-to-test faults and redundant faults, in addition to conventional stuck-at faults, is proposed. The scheme is based on applying a pair of transition patterns and observing the transition count of the transient output response of a circuit to defect faults. A fast and memory-efficient fault simulator which is based on PPSFP mechanism but can handle timing is implemented. Experimental results show that this scheme can reach a higher fault coverage than the conventional stuck-at fault testing.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130268317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design in fault isolating of ternary cellular arrays using ternary decision diagrams 基于三元决策图的三元蜂窝阵列故障隔离设计
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367230
N. Kamiura, H. Satoh, Y. Hata, K. Yamato
{"title":"Design in fault isolating of ternary cellular arrays using ternary decision diagrams","authors":"N. Kamiura, H. Satoh, Y. Hata, K. Yamato","doi":"10.1109/ATS.1994.367230","DOIUrl":"https://doi.org/10.1109/ATS.1994.367230","url":null,"abstract":"This paper proposes a method to design ternary cellular arrays with high testability. In it, stuck-at faults of switch cells are assumed. Testing of the array composed of switch cells can be executed easily because of the regular structure of the array. Moreover, if faulty cell is identified we can isolate the faulty cell from the remaining cells. The ternary functions represented by Ternary Decision Diagrams (TDD's) are realized by mapping the TDD's to the cellular arrays directly. Proposed arrays are more advantageous than ternary PLA's for their sizes in realizations of symmetric functions and are also useful for the realizations of multiple-output functions.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116847154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
C-testable multipliers based on the modified Booth algorithm 基于改进的Booth算法的c可测试乘法器
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367236
D. Gizopoulos, D. Nikolos, A. Paschalis, P. Kostarakis
{"title":"C-testable multipliers based on the modified Booth algorithm","authors":"D. Gizopoulos, D. Nikolos, A. Paschalis, P. Kostarakis","doi":"10.1109/ATS.1994.367236","DOIUrl":"https://doi.org/10.1109/ATS.1994.367236","url":null,"abstract":"In this paper we show that the conventional implementation of the multiplier based on the modified Booth algorithm with 2-bit recording is not C-testable and then we propose simple modifications that result in a C-testable design. A test set of 80 vectors is sufficient to test each cell of our multiplier exhaustively, irrespectively of its size. All single stuck-at faults are detectable with only 31 test vectors. The number of the required extra primary inputs is only two, while both the hardware and delay overhead are very small and decrease with increasing N. For example, for our C-testable design of the 64/spl times/64 multiplier, the hardware overhead is 1.60% and the delay overhead is 9.76%.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115836853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Design of random pattern testable floating point adders 随机模式可测试浮点加法器的设计
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367226
J. Rajski, J. Tyszer
{"title":"Design of random pattern testable floating point adders","authors":"J. Rajski, J. Tyszer","doi":"10.1109/ATS.1994.367226","DOIUrl":"https://doi.org/10.1109/ATS.1994.367226","url":null,"abstract":"The paper presents a floating point adder with enhanced testability and test response compaction capabilities. It is shown that the testability of the conventional adders can be improved by changing the functionality of some of their internal modules in the testing mode. It is also demonstrated that the floating point units can perform an efficient test response compaction in a built-in self test environment.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122676683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Test scheduling using test subsession partitioning 使用测试子会话分区进行测试调度
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367252
D. Xiang
{"title":"Test scheduling using test subsession partitioning","authors":"D. Xiang","doi":"10.1109/ATS.1994.367252","DOIUrl":"https://doi.org/10.1109/ATS.1994.367252","url":null,"abstract":"The tester time is expensive, which should be reduced as much as possible. Considering the fact that test response observation and test application only use a fraction of the whole testing time, a test subsession partitioning scheme is offered. Therefore, some further sources of the test scheduling problem are used. Subcircuits in conflict according to the definition are only partially in conflict now. A new test scheduling algorithm is given after the test subsession partitioning scheme is combined. This algorithm has learning ability by recording the previous conflict information, which prunes the searching space of the test scheduling problem effectively.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122879552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two techniques for minimizing power dissipation in scan circuits during test application 在测试应用过程中使扫描电路功耗最小的两种技术
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367211
S. Chakravarty, V. Dabholkar
{"title":"Two techniques for minimizing power dissipation in scan circuits during test application","authors":"S. Chakravarty, V. Dabholkar","doi":"10.1109/ATS.1994.367211","DOIUrl":"https://doi.org/10.1109/ATS.1994.367211","url":null,"abstract":"Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed. Problems required to exploit these techniques are defined. They are shown to be intractable. Heuristics required to exploit the proposed techniques are discussed. Experimental results are presented.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123444559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
A built-in self-test approach for medium to high-resolution digital-to-analog converters 内置自测试方法，用于中到高分辨率数模转换器
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367203
Karim Arabi, B. Kaminska, J. Rzeszut
{"title":"A built-in self-test approach for medium to high-resolution digital-to-analog converters","authors":"Karim Arabi, B. Kaminska, J. Rzeszut","doi":"10.1109/ATS.1994.367203","DOIUrl":"https://doi.org/10.1109/ATS.1994.367203","url":null,"abstract":"A test approach and circuitry suitable for built-in self-test (BIST) of medium to high-resolution digital-to-analog (D/A) converter are described. Offset, gain, linearity and differential linearity errors are tested without using mixed-mode or logic test equipment. The proposed BIST structure presents a compromise between test cost, area overhead and test time. The BIST circuitry has been designed using CMOS 1.2 /spl mu/m technology. The simulations performed show that the BIST is applicable for testing D/A converters up to 16-bits resolution. By a minor modification the test structure would be able to localize the fail situation and to test all D/A converters on the chip.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"30 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation 硬件加速并行模式/多故障传播并发故障仿真
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367261
W. Hahn, A. Hagerer
{"title":"Hardware-accelerated parallel-pattern/multiple-fault-propagation concurrent fault simulation","authors":"W. Hahn, A. Hagerer","doi":"10.1109/ATS.1994.367261","DOIUrl":"https://doi.org/10.1109/ATS.1994.367261","url":null,"abstract":"The Munich Simulation Computer, a highly-parallel system, has been an approach to speed up logic simulation. Most recent work, presented in this paper, has been devoted to hardware-accelerated concurrent fault simulation. By the new parallel-pattern/multiple-fault-propagation algorithm, a MuSiC version with 256 processing units can offer a simulation performance of 10/sup 8/ test-vectors times gates evaluated per second.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126655688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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