C-testable multipliers based on the modified Booth algorithm

Abstract

In this paper we show that the conventional implementation of the multiplier based on the modified Booth algorithm with 2-bit recording is not C-testable and then we propose simple modifications that result in a C-testable design. A test set of 80 vectors is sufficient to test each cell of our multiplier exhaustively, irrespectively of its size. All single stuck-at faults are detectable with only 31 test vectors. The number of the required extra primary inputs is only two, while both the hardware and delay overhead are very small and decrease with increasing N. For example, for our C-testable design of the 64/spl times/64 multiplier, the hardware overhead is 1.60% and the delay overhead is 9.76%.<>