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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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Design of pseudo-random patterns with low linear dependence and equi-distribution 低线性依赖和等分布伪随机模式的设计
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367219
S. Matsufuji, S. Tadaki, T. Yamanaka
{"title":"Design of pseudo-random patterns with low linear dependence and equi-distribution","authors":"S. Matsufuji, S. Tadaki, T. Yamanaka","doi":"10.1109/ATS.1994.367219","DOIUrl":"https://doi.org/10.1109/ATS.1994.367219","url":null,"abstract":"Pseudo-random patterns with equi-distribution given by some phase-shifted M-sequences are often used to produce random numbers used in simulations and test patterns in VLSI tests. Low linear dependency is one of the desirable and important properties of random patterns as well as equi-distribution. This paper discusses pseudo-random patterns with equi-distribution and low linear dependence.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127367161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluations of various TPG circuits for use in two-pattern testing 用于双模试验的各种TPG电路的评估
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367224
K. Furuya, S. Yamazaki, M. Sato
{"title":"Evaluations of various TPG circuits for use in two-pattern testing","authors":"K. Furuya, S. Yamazaki, M. Sato","doi":"10.1109/ATS.1994.367224","DOIUrl":"https://doi.org/10.1109/ATS.1994.367224","url":null,"abstract":"Transition coverage has already been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117104012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficiency improvements for multiple fault diagnosis of combinational circuits 组合电路多重故障诊断效率的提高
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367249
N. Yanagida, H. Takahashi, Y. Takamatsu
{"title":"Efficiency improvements for multiple fault diagnosis of combinational circuits","authors":"N. Yanagida, H. Takahashi, Y. Takamatsu","doi":"10.1109/ATS.1994.367249","DOIUrl":"https://doi.org/10.1109/ATS.1994.367249","url":null,"abstract":"We present two techniques for improving the efficiency of the previous method for multiple fault diagnosis of combinational circuits. (1) Three new rules for deducing the valves at the internal lines are added to the previous deduction rules. Experimental results show that 2.6/spl sim/15.2% improvements in resolution are achieved by adding the enhanced deduction rules without probing the internal lines. (2) A probing method for diagnosis is proposed to improve the resolution obtained by the method (1). Preliminary experimental results show that about 0.1/spl sim/9.4% improvements in resolution are further achieved by probing about 4/spl sim/111 internal lines in the circuit.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124566062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A unified method for assembling global test schedules 装配全局测试计划的统一方法
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367220
A. P. Stroele, H. Wunderlich
{"title":"A unified method for assembling global test schedules","authors":"A. P. Stroele, H. Wunderlich","doi":"10.1109/ATS.1994.367220","DOIUrl":"https://doi.org/10.1109/ATS.1994.367220","url":null,"abstract":"In order to make a register transfer structure testable, it is usually divided into functional blocks that can be tested independently by various test methods. The test patterns are shifted in or generated autonomously at the inputs of each block. The test responses of a block are compacted or observed at its output register. In this paper a unified method for assembling all the single tests to a global schedule is presented. It is compatible with a variety of different test methods. The described scheduling procedures reduce the overall test time and minimize the number of internal registers that have to be made directly observable.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129206673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A partial scan algorithm based on reduced scan shift 一种基于减小扫描位移的部分扫描算法
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367209
Y. Higami, S. Kajihara, K. Kinoshita
{"title":"A partial scan algorithm based on reduced scan shift","authors":"Y. Higami, S. Kajihara, K. Kinoshita","doi":"10.1109/ATS.1994.367209","DOIUrl":"https://doi.org/10.1109/ATS.1994.367209","url":null,"abstract":"This paper presents a partial scan algorithm, called PARES (Partial scan Algorithm based on REduced Scan shift), which designs partial scan circuits and generates short test sequences. PARES is based on the reduced scan shift, in which flip flops (FFs) required to be controlled and observed are determined for each test vector in order to reduce scan shift operations. PARES selects FFs which are more frequently required to be controlled or observed as a scanned FF. Short test sequence can be obtained by reducing scan shift operations. Since fault coverage may be not possibly high because of unscanned FFs, techniques to increase fault coverage are also proposed. The order of test vectors are determined such that the values of unscanned FFs after applying a test vector is equivalent to next applied test vector. Moreover, appropriate values are assigned to primary inputs in scan shift operations in order to detect more faults. Finally experimental results for ISCAS'89 benchmark circuits are given.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123996021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Bounding error masking in linear output space compression schemes 线性输出空间压缩方案中的边界误差掩蔽
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367258
S. Tarnick
{"title":"Bounding error masking in linear output space compression schemes","authors":"S. Tarnick","doi":"10.1109/ATS.1994.367258","DOIUrl":"https://doi.org/10.1109/ATS.1994.367258","url":null,"abstract":"Based on the principle of linear output space compression we present a design method for concurrent checkers such that the masking probability of errors caused by faults of a given set of circuit faults is below a given bound, while keeping the space compression ratio, defined as the ratio of the number of circuit outputs to the number of outputs of the space compressor, as high as possible. Experiments performed on the ISCAS-85 benchmark circuits show that the compression ratios achieved with compression functions computed with this method can be very high, even for very low bounds for the error masking probability and large fault sets.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131699361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Gate-level design diagnosis using a learning-based search strategy 使用基于学习的搜索策略的门级设计诊断
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367222
I. Pomeranz, S. Reddy
{"title":"Gate-level design diagnosis using a learning-based search strategy","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1994.367222","DOIUrl":"https://doi.org/10.1109/ATS.1994.367222","url":null,"abstract":"We propose a procedure for performing design error diagnosis at the gate level. The procedure is applicable to circuits having size parameters. It is based on the search strategy INCREDYBLE introduced before. The unique features of this procedure are that its performance does not deteriorate with circuit size, and that it is able to correct large numbers of errors present in the circuit at the same time. We demonstrate the procedure and provide experimental evidence of its effectiveness.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128904511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testable synthesis and testing of finite state machines 有限状态机的可测试综合与测试
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367214
Chen-Yeh Liu, K. Saluja
{"title":"Testable synthesis and testing of finite state machines","authors":"Chen-Yeh Liu, K. Saluja","doi":"10.1109/ATS.1994.367214","DOIUrl":"https://doi.org/10.1109/ATS.1994.367214","url":null,"abstract":"In this paper, me outline a method for testable synthesis of finite state machines (FSMs). We address the design for testability issue for testing FSMs with and without scan. The experimental results on the MCNC benchmarks show that our designs are 100% testable with small to moderate increase in area.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114339021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Fault coverage analysis in monitored sequential circuits 时序监控电路的故障覆盖分析
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367257
R. Parekhji, G. Venkatesh, S. Sherlekar
{"title":"Fault coverage analysis in monitored sequential circuits","authors":"R. Parekhji, G. Venkatesh, S. Sherlekar","doi":"10.1109/ATS.1994.367257","DOIUrl":"https://doi.org/10.1109/ATS.1994.367257","url":null,"abstract":"This paper discusses the fault detection capabilities of monitored synchronous sequential circuits. Here a monitoring machine operates in lock-step with the main machine. This approach has two desirable features for fault detection. Besides the monitoring machine being less costly than the main machine, it is also not identical to it. It is shown that these features result in an improved fault coverage, of simultaneous delay faults affecting both the machines, as compared to duplication. At the same time, the hardware cost of the monitored sequential circuit is significantly lower.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114919700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio 门间和门内CMOS桥接故障的统一模型:配置比
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367235
M. Renovell, P. Huc, Y. Bertrand
{"title":"A unified model for inter-gate and intra-gate CMOS bridging fault: the configuration ratio","authors":"M. Renovell, P. Huc, Y. Bertrand","doi":"10.1109/ATS.1994.367235","DOIUrl":"https://doi.org/10.1109/ATS.1994.367235","url":null,"abstract":"In order to simulate the effects of a bridging fault it is necessary to accurately determine the intermediate voltage of the shorted nodes and compare it to the logic threshold voltage of the driven gates. This paper presents a general model called \"the configuration ratio model\" which can be used to determine if a particular structure of transistors gives an intermediate voltage which is higher or lower than a given threshold voltage. This general model applies to inter-gate and intra-gate bridging fault. Moreover the approach is extremely faster than the previous ones since no SPICE simulation is required. The accuracy is of 0.06 V to compare with SPICE simulations.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117195792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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