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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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A genetic approach to test generation for logic circuits 逻辑电路测试生成的遗传方法
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367246
T. Hayashi, H. Kita, K. Hatayama
{"title":"A genetic approach to test generation for logic circuits","authors":"T. Hayashi, H. Kita, K. Hatayama","doi":"10.1109/ATS.1994.367246","DOIUrl":"https://doi.org/10.1109/ATS.1994.367246","url":null,"abstract":"This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic approach is effective for solving test generation problem.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121420491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Fault diagnosis technique for subranging ADCs 分插式adc故障诊断技术
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367204
Anchada Charoenrmk, Mani Soma
{"title":"Fault diagnosis technique for subranging ADCs","authors":"Anchada Charoenrmk, Mani Soma","doi":"10.1109/ATS.1994.367204","DOIUrl":"https://doi.org/10.1109/ATS.1994.367204","url":null,"abstract":"This paper describes a fault diagnosis technique for subranging analog to digital converters (ADCs). Functional fault in each of the analog component in the subranging ADC affects the transfer function differently. This property is employed for fault diagnosis. Deviation from ideal of the transfer function which is categorized into offset error, gain error, DNL, and INL data, are used for fault diagnosis. The technique is therefore not dependent on the test method, and it can be applied to dynamic test data. The diagnosis procedure is presented in detail. Simulation results and a case study are also presented. They verify the diagnosis technique.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis 基于电源电流监测和判别分析的模拟集成电路测试
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367242
Z. Wang, G. Gielen, W. Sansen
{"title":"Testing of analog integrated circuits based on power-supply current monitoring and discrimination analysis","authors":"Z. Wang, G. Gielen, W. Sansen","doi":"10.1109/ATS.1994.367242","DOIUrl":"https://doi.org/10.1109/ATS.1994.367242","url":null,"abstract":"A new method for the testing and fault detection of analog integrated circuits is presented. The power-supply current is monitored to detect possible faults in an analog circuit. The spectrum of the power-supply current is used to construct the statistical signature of the fault-free and faulty circuits. The decision of a circuit being fault-free or faulty is taken based on the Bayes decision rule fully taking into account the tolerances on the circuit parameters. Examples are given to show the efficiency and effectiveness of the algorithm.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126867888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Easily testable realizations for generalized Reed-Muller expressions 易于测试的实现广义Reed-Muller表达式
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367237
Tsutomu Sasao
{"title":"Easily testable realizations for generalized Reed-Muller expressions","authors":"Tsutomu Sasao","doi":"10.1109/ATS.1994.367237","DOIUrl":"https://doi.org/10.1109/ATS.1994.367237","url":null,"abstract":"This paper presents a design method of easily testable AND-EXOR networks. It is an improvement of Reddy and Saluja-Reddy's methods, and has the following features: 1) The network consists of a literal part, an AND part, an EXOR part, and a check part; 2) The EXOR part can be a tree instead of a cascade. Thus, the network is faster; 3) The network uses generalized Reed-Muller expressions (GRMs) instead of Positive Polarity Reed-Muller expressions (PPRMs). The number of products for GRMs is, on the average, less than a half of that for PPRMs, and is less than that of sum-of-products expression (SOPs); 4) The test detects multiple stuck-at-faults under the assumption that the faults occur in at most one part, either the literal part, the AND part, the EXOR part, or the check part.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115246146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
Analysis and improvement of testability measure approximation algorithms 可测性测度近似算法的分析与改进
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367233
J. Bitner, J. Jain, J. Abraham, D. Fussell
{"title":"Analysis and improvement of testability measure approximation algorithms","authors":"J. Bitner, J. Jain, J. Abraham, D. Fussell","doi":"10.1109/ATS.1994.367233","DOIUrl":"https://doi.org/10.1109/ATS.1994.367233","url":null,"abstract":"This paper presents a theoretical framework for the study of algorithms for approximating testability measures. To illustrate its application, we consider two well-known algorithms. It is shown empirically that both algorithms perform very poorly on several circuits of realistic size. For some circuits, an equally good approximation to the testability measure can be achieved by a random number generator or a \"0th order\" approximation algorithm that always returns a constant 1/2. Analytically, we present several circuits for which the performance of these algorithms is arbitrarily bad. The analysis is then used to identify their weaknesses, and procedures are suggested through which such unpredictable performances may be improved. One procedure is discussed in detail and an order of magnitude improvement in accuracy results.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131586817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient test sequence generation for localization of multiple faults in communication protocols 针对通信协议中多故障定位的高效测试序列生成
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367228
Y. Kakuda, H. Yukitomo, S. Kusumoto, T. Kikuno
{"title":"Efficient test sequence generation for localization of multiple faults in communication protocols","authors":"Y. Kakuda, H. Yukitomo, S. Kusumoto, T. Kikuno","doi":"10.1109/ATS.1994.367228","DOIUrl":"https://doi.org/10.1109/ATS.1994.367228","url":null,"abstract":"Conformance test for communication protocols is indispensable for the production of reliable communications software. A lot of conformance test techniques have been developed. However, most of them can only decide whether an implemented protocol conforms to its specification. That is, the exact locations of faults are not determined by them. This paper presents some conditions that enable to find location of multiple faults, and then proposes a test sequence generation technique under such conditions. The characteristics of this technique are to generate test sequences based on protocol specifications and interim test results, and to find locations of multiple faults in protocol implementations. Although the length of the test sequence generated by the proposed technique is a little longer than the one generated by the previous one, the class to which the proposed technique can be applied is larger than that to which the previous one can be applied.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132807596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experiments of faults on the "Happa" system and a proposal of backup RAM technique “Happa”系统的故障实验及备份RAM技术的提出
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367208
K. Iwasaki, H. Yoshikawa, A. Furuta
{"title":"Experiments of faults on the \"Happa\" system and a proposal of backup RAM technique","authors":"K. Iwasaki, H. Yoshikawa, A. Furuta","doi":"10.1109/ATS.1994.367208","DOIUrl":"https://doi.org/10.1109/ATS.1994.367208","url":null,"abstract":"On the \"Happa\" parallel microcomputer system, faults were experimentally examined for the boundary of its operating range. Global bus faults, torus communication faults, and others were observed. A backup RAM technique is proposed for bus faults.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides 用交换网络和神经算法重建两侧有备件的网格连接处理器阵列
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367205
I. Takanami, Y. Hisanaga, K. Inoue
{"title":"Switching networks and neural algorithms for reconstructing mesh-connected processor arrays with spares on their sides","authors":"I. Takanami, Y. Hisanaga, K. Inoue","doi":"10.1109/ATS.1994.367205","DOIUrl":"https://doi.org/10.1109/ATS.1994.367205","url":null,"abstract":"First, we present switching networks and a reconstruction strategy for mesh-connected processor arrays with linear arrays of spares on their left/right/upper/bottom sides. Each faulty processor is compensated by a spare on any one of left/right/upper/bottom sides. The reconstruction is done by shifting vertically first and then horizontally. Such a new reconstruction strategy leads to the simple and systematic switching operations for the networks. The networks are regular and comparatively simple. The distances between logically adjacent processors after the reconstruction are bounded by a constant. Next, we describe exhaustive algorithms for reconstruction. It seems that efficient ones can not be found. So, using a Hopfield-type neural network model, we present algorithms for the two cases where the linear arrays of spares are on the right and bottom sides, and on the right and left and bottom sides, and show their effectiveness by computer simulation.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115516946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design verification by using universal test sets 使用通用测试集进行设计验证
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367221
Beyin Chen, Chong Len Lee, J. Chen
{"title":"Design verification by using universal test sets","authors":"Beyin Chen, Chong Len Lee, J. Chen","doi":"10.1109/ATS.1994.367221","DOIUrl":"https://doi.org/10.1109/ATS.1994.367221","url":null,"abstract":"In this paper, the application of universal test sets (UTS) to design verification is studied. First, the paper analyzes the relationships between the design error models and the stuck-at fault model. Then theorems are presented to show that the UTS can detect almost all the design errors. Experimental results show that design verification using UTS is an efficient approach.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128694659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Minimum test sets for locally exhaustive testing of combinational circuits with five outputs 具有五个输出的组合电路局部穷举测试的最小测试集
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367218
T. Yokohira, T. Shimizu, H. Michinishi, Y. Sugiyama, T. Okamoto
{"title":"Minimum test sets for locally exhaustive testing of combinational circuits with five outputs","authors":"T. Yokohira, T. Shimizu, H. Michinishi, Y. Sugiyama, T. Okamoto","doi":"10.1109/ATS.1994.367218","DOIUrl":"https://doi.org/10.1109/ATS.1994.367218","url":null,"abstract":"In this paper, features of dependence matrices of combinational circuits with five outputs are discussed, and it is shown that a minimum test set for locally exhaustive testing of such circuits always has 2/sup w/ test patterns, where w is the maximum number of inputs on which any output depends.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127168268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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