A genetic approach to test generation for logic circuits

Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI:10.1109/ATS.1994.367246

T. Hayashi, H. Kita, K. Hatayama

引用次数: 8

Abstract

This paper presents a genetic algorithm to generate tests for logic circuits. Bit strings corresponding to primary input patterns are evolved into tests for detecting a target fault by genetic operations. Some new techniques, such as a crossover operation based on fault-excitability and fault-drivability, are introduced to achieve high fault coverage. Experimental results show that the genetic approach is effective for solving test generation problem.<>

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逻辑电路测试生成的遗传方法

本文提出了一种用于逻辑电路测试生成的遗传算法。通过遗传运算，将主输入模式对应的位串演化为检测目标故障的测试。为了实现高故障覆盖率，引入了基于故障可激性和故障可驱动性的交叉操作等新技术。实验结果表明，遗传算法是解决测试生成问题的有效方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of IEEE 3rd Asian Test Symposium (ATS)

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