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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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To verify manufacturing yield by testing 通过测试来验证生产成品率
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367201
Mill-Jer Wang, Jwu E. Chen, Yung-Yuan Chen
{"title":"To verify manufacturing yield by testing","authors":"Mill-Jer Wang, Jwu E. Chen, Yung-Yuan Chen","doi":"10.1109/ATS.1994.367201","DOIUrl":"https://doi.org/10.1109/ATS.1994.367201","url":null,"abstract":"The effect of test errors should be cancelled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the yield data obtained from engineering stage, the upper and lower bounds of chip yield are calculated after determining the variance of defect density and clustering parameter. The yield bound/distribution is used to diagnose the results after wafer sort while in production. One ASIC product is used to validate this yield analysis procedure. This work can assist the ASIC design center to determine a manufacturing laboratory beginning the design and to control the chip area in the period of circuit design.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Automatic program generator for simulation-based processor verification 用于基于仿真的处理器验证的自动程序生成器
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367215
H. Iwashita, S. Kowatari, T. Nakata, F. Hirose
{"title":"Automatic program generator for simulation-based processor verification","authors":"H. Iwashita, S. Kowatari, T. Nakata, F. Hirose","doi":"10.1109/ATS.1994.367215","DOIUrl":"https://doi.org/10.1109/ATS.1994.367215","url":null,"abstract":"This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128775002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Test time reduction for scan-designed circuits by sliding compatibility 通过滑动兼容性减少扫描设计电路的测试时间
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367210
Jau-Shien Chang, Chen-Shang Lin
{"title":"Test time reduction for scan-designed circuits by sliding compatibility","authors":"Jau-Shien Chang, Chen-Shang Lin","doi":"10.1109/ATS.1994.367210","DOIUrl":"https://doi.org/10.1109/ATS.1994.367210","url":null,"abstract":"A post generation method for test time reduction of scan-designed circuits is developed in this paper. Maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity-scan, the test clocks required by our developed method are only 41% of those reported by H. Fujiwara and A. Yamamoto (1993).<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124176830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characteristics of a fuzzy test system 模糊测试系统的特点
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367202
T. Koyama
{"title":"Characteristics of a fuzzy test system","authors":"T. Koyama","doi":"10.1109/ATS.1994.367202","DOIUrl":"https://doi.org/10.1109/ATS.1994.367202","url":null,"abstract":"Stable outgoing quality is assured by using a test system with a fuzzy controller, even when sudden changes of incoming quality occur. Non test is automatically selected, when incoming quality becomes far better than a target quality. The author studies how to check the stability condition of the fuzzy test system. The condition is that the value, the sample size at the t-th test divided by the size of lot products, is smaller than that, the outgoing quality at (t-1)-th test by incoming quality.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114554829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test generation for redundant faults in combinational circuits by using delay effects 利用延迟效应产生组合电路中冗余故障的测试
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367245
X. Yu, Hiroshi Takahashi, Y. Takamatsu
{"title":"Test generation for redundant faults in combinational circuits by using delay effects","authors":"X. Yu, Hiroshi Takahashi, Y. Takamatsu","doi":"10.1109/ATS.1994.367245","DOIUrl":"https://doi.org/10.1109/ATS.1994.367245","url":null,"abstract":"Practical combinational circuits include some undetectable stuck-at faults called the redundant faults. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, we study the testing problem of the redundant fault in the combinational circuit by using delay effects and propose a method for generating a test-pair of a redundant fault. By using an extended seven-valued calculus, the proposed method generates a dynamically sensitizable path which includes a target redundant fault on a restricted single path. The dynamically sensitizable path will propagate the effect of the target redundant fault to the output of the circuit by the delay effects. Preliminary experiments on the benchmark circuits show that test-pairs for some redundant faults are generated theoretically.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125246949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A built-in I/sub DDQ/ test circuit utilizing upper and lower limits 内置I/sub DDQ/测试电路，利用上限和下限
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367240
Y. Miura, S. Naito
{"title":"A built-in I/sub DDQ/ test circuit utilizing upper and lower limits","authors":"Y. Miura, S. Naito","doi":"10.1109/ATS.1994.367240","DOIUrl":"https://doi.org/10.1109/ATS.1994.367240","url":null,"abstract":"A test circuit for the built-in I/sub DDQ/ testing is proposed. The circuit can use two current values, an upper limit and a lower limit, to judge whether CUT is fault-free or not. The test circuit is applicable to fault detection for both digital and analog circuits. We show the efficiency of the test circuit using SPICE3 simulator.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient fault ordering for automatic test pattern generation for sequential circuits 时序电路测试模式自动生成的有效故障排序
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367244
P. A. Krauss, M. Henftling
{"title":"Efficient fault ordering for automatic test pattern generation for sequential circuits","authors":"P. A. Krauss, M. Henftling","doi":"10.1109/ATS.1994.367244","DOIUrl":"https://doi.org/10.1109/ATS.1994.367244","url":null,"abstract":"This paper analyzes fault dependency in sequential circuits to accelerate parallel automatic test pattern generation (ATPG). We present the new algorithms improved fault collapsing and fault arranging for an efficient fault ordering to speedup ATPG. Experimental results obtained for sequential and fault parallel ATPG show the efficiency of the proposed methods.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"2 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123674837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Automatic test generation for functional verification of microprocessors 微处理器功能验证的自动测试生成
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367216
J. Miyake, G. Brown, M. Ueda, T. Nishiyama
{"title":"Automatic test generation for functional verification of microprocessors","authors":"J. Miyake, G. Brown, M. Ueda, T. Nishiyama","doi":"10.1109/ATS.1994.367216","DOIUrl":"https://doi.org/10.1109/ATS.1994.367216","url":null,"abstract":"A novel method to generate test programs for functional verification of microprocessors is presented. The method combines schemes of random generation and specific sequence generation. Four levels of hierarchical information are used to generate efficient test programs including many complicated sequences. Considerations in the test generation is also discussed.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131300513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An efficient logical fault diagnosis for combinational circuits using stuck-at fault simulation 基于卡滞故障仿真的有效组合电路逻辑故障诊断
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367250
T. Shimino
{"title":"An efficient logical fault diagnosis for combinational circuits using stuck-at fault simulation","authors":"T. Shimino","doi":"10.1109/ATS.1994.367250","DOIUrl":"https://doi.org/10.1109/ATS.1994.367250","url":null,"abstract":"A new efficient method to diagnose faults in a gate or function block is proposed. This method can localize a single logic function fault, which is caused by internal stuck-at, short or open faults in the gate or function block, by using stuck-at fault simulation. Since a practical fault diagnostic system is now under development the effectiveness of the method is demonstrated by experimental results on the ISCAS'85 benchmark circuits.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"17 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120929082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and evaluation of fault-tolerant interleaved memory systems 容错交错存储系统的设计与评价
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367206
S. Kuo, A. Louri, Sheng-Chiech Liang
{"title":"Design and evaluation of fault-tolerant interleaved memory systems","authors":"S. Kuo, A. Louri, Sheng-Chiech Liang","doi":"10.1109/ATS.1994.367206","DOIUrl":"https://doi.org/10.1109/ATS.1994.367206","url":null,"abstract":"A highly reliable interleaved memory system for uniprocessor and multiprocessor computer architectures is presented. The memory system is divided into groups. Each group consists of several banks and furthermore, each bank has several memory units. Spare memory units as well as spare banks are incorporated in the system to enhance reliability. Reliability figures are derived to evaluate systems with various amounts of redundancy. The result shows that the system reliability can be significantly improved with little hardware overhead. User transparency in memory access is retained.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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