用于基于仿真的处理器验证的自动程序生成器

Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI:10.1109/ATS.1994.367215

H. Iwashita, S. Kowatari, T. Nakata, F. Hirose

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引用次数: 1

摘要

本文提出了一种有效的逻辑仿真测试程序生成器，它使用了为形式验证而开发的技术。我们的测试程序生成器枚举处理器管道的所有可到达状态，并为任何可到达的测试用例生成指令序列。该程序涵盖了所有复杂的测试用例，这些用随机指令很难涵盖，用传统的测试程序生成方法也不可能涵盖。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Automatic program generator for simulation-based processor verification

This paper presents an efficient test program generator for logic simulation that uses techniques developed for formal verification. Our test program generator enumerates all reachable states of a processor pipeline and generates instruction sequences for any reachable test case. The program covers all complicated test cases that are difficult to cover with random instructions and are impossible to cover by conventional test program generation methods.<>

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Proceedings of IEEE 3rd Asian Test Symposium (ATS)

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