通过测试来验证生产成品率

Mill-Jer Wang, Jwu E. Chen, Yung-Yuan Chen
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引用次数: 3

摘要

在利用试验良率分析制造良率之前,应消除试验误差的影响。测试错误可以从工程运行和生产运行阶段得到缓解。成品率建模的一个比较困难的方面是缺陷密度通常不是随时间恒定的。本文研究了在生产试验中使用缺陷监视器的流程。基于工程阶段获得的良率数据,确定缺陷密度方差和聚类参数方差,计算出晶片良率的上下界。产率界/分布用于生产中晶圆分选后的结果诊断。一个ASIC产品被用来验证这个良率分析程序。这项工作可以帮助ASIC设计中心确定开始设计的制造实验室,并在电路设计期间控制芯片面积。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
To verify manufacturing yield by testing
The effect of test errors should be cancelled while before test yield is used to analyze the manufacturing yield. Test errors can be alleviated from engineering run and production run stages. One of the more difficult aspect of yield modeling is the fact that defect density is generally not constant with time. In this paper, we study the flow of defect monitor used in production test. Based on the yield data obtained from engineering stage, the upper and lower bounds of chip yield are calculated after determining the variance of defect density and clustering parameter. The yield bound/distribution is used to diagnose the results after wafer sort while in production. One ASIC product is used to validate this yield analysis procedure. This work can assist the ASIC design center to determine a manufacturing laboratory beginning the design and to control the chip area in the period of circuit design.<>
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