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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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A new testable design of logic circuits under highly observable condition 一种新的逻辑电路在高度可观测条件下的可测试设计
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367231
W. Xiaoqing, H. Tamamoto, K. Kinoshita
{"title":"A new testable design of logic circuits under highly observable condition","authors":"W. Xiaoqing, H. Tamamoto, K. Kinoshita","doi":"10.1109/ATS.1994.367231","DOIUrl":"https://doi.org/10.1109/ATS.1994.367231","url":null,"abstract":"This paper presents the concept of k-FR circuits. It is shown that all stuck-at faults and stuck-open faults in a k-FR circuit can be detected and located by k(k+1)+1 tests render the highly observable condition. K is usually two or three. The paper also presents an algorithm for converting an arbitrary combinational circuit into a k-FR circuit.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134355196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Testability considerations in technology mapping 技术映射中的可测试性考虑
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367238
I. Pomeranz, S. Reddy
{"title":"Testability considerations in technology mapping","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1994.367238","DOIUrl":"https://doi.org/10.1109/ATS.1994.367238","url":null,"abstract":"We consider the problem of incorporating testability into the process of technology mapping. We demonstrate through examples that the testability of technology mapped circuits depends on the technology mapping process, and can be controlled during this process. We then introduce the required concepts to perform technology mapping with testability considerations. We propose a specific technology mapping procedure that accommodates testability as a criterion for selecting the mapping, and present experimental results to demonstrate the tradeoff between area and testability. We also propose a Design-For-Testability procedure that can be incorporated into the technology mapping procedure, and can guarantee complete fault coverage.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132822883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
The effect of fault detection by IDDq measurement for CMOS VLSIs IDDq测量对CMOS vlsi故障检测的影响
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367239
J. Hirase, M. Hamada
{"title":"The effect of fault detection by IDDq measurement for CMOS VLSIs","authors":"J. Hirase, M. Hamada","doi":"10.1109/ATS.1994.367239","DOIUrl":"https://doi.org/10.1109/ATS.1994.367239","url":null,"abstract":"In the final stages of VLSI testing, improved quality VLSI testing is an important subject for ensuring reliability in the forwarded VLSI market. On the other hand, developments in high integration technology have resulted in an increased number of blocks in VLSI devices and an increased number of gates for each terminal. Consequently, it has become more difficult to improve the quality of VLSI tests. We have developed a new test method in addition to conventional testing methods intended for improving the test coverage in VLSI tests. This new test method analyzes the relationship between IDDq (Quiescent Power Supply Current) of DUT and DUT failure by applying the concept of the toggle rate. Accordingly, in this paper we report that the results of IDDq testing confirm a correlation with defect level.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"380 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116620981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Random test input generation for supply current testing of TTL combinational circuits 用于TTL组合电路供电电流测试的随机测试输入生成
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367241
M. Hashizume, I. Tsukimoto, T. Tamesada
{"title":"Random test input generation for supply current testing of TTL combinational circuits","authors":"M. Hashizume, I. Tsukimoto, T. Tamesada","doi":"10.1109/ATS.1994.367241","DOIUrl":"https://doi.org/10.1109/ATS.1994.367241","url":null,"abstract":"In this paper, a random test generation algorithm for supply current testing of TTL combinational circuits is proposed. In this method, by inserting equivalent faults first in the direction from the primary output ports to the primary input ports, the total number of fault simulations can be decreased. In this paper it is shown that test input vector can be derived more quickly by means of the algorithm.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124774279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Software design verification using FTA 软件设计验证使用FTA
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367229
T. Fukuya, M. Hirayama, Y. Mihara
{"title":"Software design verification using FTA","authors":"T. Fukuya, M. Hirayama, Y. Mihara","doi":"10.1109/ATS.1994.367229","DOIUrl":"https://doi.org/10.1109/ATS.1994.367229","url":null,"abstract":"We propose a verification approach for software specification. In order to avoid software design faults, our approach derives safety assertions using fault tree analysis, computes a behavioral graph of specification and analyzes statically whether this graph satisfies safety assertions. When there exists an assertion which can not hold, our method localizes software design faults. Moreover we show an example of our approach applied to a practical \"microwave oven\" development.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Selecting programmable space compactors for BIST using genetic algorithms 利用遗传算法选择可编程空间压缩器
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367225
Barry K. Tsuji, A. Ivanov, Y. Zorian
{"title":"Selecting programmable space compactors for BIST using genetic algorithms","authors":"Barry K. Tsuji, A. Ivanov, Y. Zorian","doi":"10.1109/ATS.1994.367225","DOIUrl":"https://doi.org/10.1109/ATS.1994.367225","url":null,"abstract":"With the increasing complexity of modern VLSI circuits, achieving high duality (off-line) built-in self-test requires monitoring an increasingly large number of internal nodes. Due to the limitations in observing large numbers of nodes, it has become increasingly necessary to compact the output from a large number of lines to a small number of lines in a process known as space compaction. Recently, a class of circuit-specific space compactors, known as programmable space compactors (PSCs), has been proposed. Circuit-specific information such as the fault-free and expected faulty behaviour of a circuit can be used to choose PSCs that have better fault coverage and/or lower area costs than the parity function. A drawback of PSCs is the difficulty involved in finding optimal PSCs for a circuit, since the space of possible PSC functions is extremely large and grows exponentially with the number of lines to be compacted. This paper proposes a method for searching for combinational PSCs based upon genetic algorithms. The factors used to assess the effectiveness, or fitness, of a PSC are its fault coverage (estimated by the probability of aliasing) and area. Searches based upon genetic algorithms can find PSCs with better fault coverage and cost characteristics than the parity function using modest computing resources. PSCs with equal or greater fault coverage than the parity function for as little as 20% of the cost (in terms of gate count) were found with an investment of only a few hours of workstation computing time.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Time-space modal model checking towards verification of bit-slice architecture 面向位片结构验证的时空模态模型检验
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367217
Hiromi Hiraishi
{"title":"Time-space modal model checking towards verification of bit-slice architecture","authors":"Hiromi Hiraishi","doi":"10.1109/ATS.1994.367217","DOIUrl":"https://doi.org/10.1109/ATS.1994.367217","url":null,"abstract":"The goal of this paper is to propose a new symbolic model checking approach named time-space modal modal checking, which could be applicable to verification of bit-slice microprocessor of infinite bit width and one dimensional systolic array of infinite length. A simple benchmark result shows the effectiveness of the proposed approach.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123384897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of byte error detecting codes to the design of self-checking circuits 字节错误检测码在自检电路设计中的应用
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367256
S. Pagey, A. Al-Khalili
{"title":"Application of byte error detecting codes to the design of self-checking circuits","authors":"S. Pagey, A. Al-Khalili","doi":"10.1109/ATS.1994.367256","DOIUrl":"https://doi.org/10.1109/ATS.1994.367256","url":null,"abstract":"In this paper, we discuss the application of byte error detecting codes to the design of self-checking circuits for the single stuck-at fault model. We discuss strongly fault-secure realization of a given Boolean function using byte error detecting codes. Even though parity is the most efficient separable code for the detection of single errors, we show that the use of a byte error detecting code can lead to lower cost of self-checking realization of a given function as compared to its self-checking realization using the parity code. We also present a method for the design of totally self-checking checkers for byte error detecting codes. Experimental results obtained for various test circuits are also discussed.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128952442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test generation and fault simulation algorithms for sequential circuits with embedded RAMs 嵌入式ram顺序电路的测试生成和故障仿真算法
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367262
T. Chakraborty, V. Agrawal
{"title":"Test generation and fault simulation algorithms for sequential circuits with embedded RAMs","authors":"T. Chakraborty, V. Agrawal","doi":"10.1109/ATS.1994.367262","DOIUrl":"https://doi.org/10.1109/ATS.1994.367262","url":null,"abstract":"In this paper, novel algorithms are given for test generation and fault simulation for sequential circuits with embedded RAMs. Stuck-at faults are propagated through these RAMs that are represented as functional models. While only faults on the input and output data lines are targeted for test generation, all faults of the RAM model, including the faults on the address and read/write lines are, simulated. A dynamic and very efficient memory management scheme is proposed to store the faulty values in the embedded RAMs during fault simulation. Although the test generation algorithm is not a complete algorithm, most address and read/write faults are detected during fault simulation of test vectors generated for other faults. Results indicate that high fault coverage can be achieved for practical circuits. A proposed design for testability requires scanning of only the address and read/write lines of RAMs.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117220884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A diagnostic network for massively parallel processing systems 用于大规模并行处理系统的诊断网络
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367207
Yoon-Hwa Choi, Yu-Seok Kim
{"title":"A diagnostic network for massively parallel processing systems","authors":"Yoon-Hwa Choi, Yu-Seok Kim","doi":"10.1109/ATS.1994.367207","DOIUrl":"https://doi.org/10.1109/ATS.1994.367207","url":null,"abstract":"Massively parallel processing systems consist of a large number of processing nodes to provide high performance primarily for data-intensive applications. In a system of such dimensions high availability cannot be achieved without relying on redundancy and reconfiguration. An important aspect of highly available design is rapid diagnosis and graceful degradation in the event of a failure. This paper presents a diagnostic network for locating faults in massively parallel processing systems comprised of identical processing nodes.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124165595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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