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Proceedings of IEEE 3rd Asian Test Symposium (ATS)最新文献

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Data path synthesis for easy testability 数据路径合成，便于测试
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367212
M. Dhodhi, I. Ahmad, A. Ismaeel
{"title":"Data path synthesis for easy testability","authors":"M. Dhodhi, I. Ahmad, A. Ismaeel","doi":"10.1109/ATS.1994.367212","DOIUrl":"https://doi.org/10.1109/ATS.1994.367212","url":null,"abstract":"Synthesizing digital circuits which can be easily tested is an important and necessary aspect of a useful behavioral synthesis system. Testability at behavioral level can be enhanced by minimizing the number of self-adjacent registers (self-loops). This paper describes a technique for synthesizing an easy testable (loop-free) data path structure from a behavioral description of a design. The synthesis process uses an approach based on a problem-space genetic algorithm (PSGA) to perform concurrent scheduling and allocation of testable functional units to eliminate the self-loops. Experiments on benchmarks show that the self-loops can be eliminated with a minimum additional hardware resources to result in a testable data path.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114067338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Efficient diagnostic fault simulation for sequential circuits 时序电路的高效诊断故障仿真
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367247
J. Jou, Shung-Chih Chen
{"title":"Efficient diagnostic fault simulation for sequential circuits","authors":"J. Jou, Shung-Chih Chen","doi":"10.1109/ATS.1994.367247","DOIUrl":"https://doi.org/10.1109/ATS.1994.367247","url":null,"abstract":"In this paper, an efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus reduces a great deal of diagnostic comparisons among all pairs of faults. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault correctly. Experimental results show that our method achieves a significant speedup compared to previous methods.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114255477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Detectability of spurious signals with limited propagation in combinational circuits 组合电路中有限传播杂散信号的可检测性
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367232
F. Moll, M. Roca, D. Marche, A. Rubio
{"title":"Detectability of spurious signals with limited propagation in combinational circuits","authors":"F. Moll, M. Roca, D. Marche, A. Rubio","doi":"10.1109/ATS.1994.367232","DOIUrl":"https://doi.org/10.1109/ATS.1994.367232","url":null,"abstract":"The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation limits of crosstalk signals has been developed for combinational circuits. An algorithm for crosstalk faults test pattern generation is proposed taking into account the propagation limitation of the signals. Results of the implementation of the algorithm are shown, putting into evidence the dependency of the detectability of spurious signals on their propagation limits.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114317412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Strongly fail-safe interfaces based on concurrent checking 基于并发检查的强故障安全接口
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367255
M. Nicolaidis
{"title":"Strongly fail-safe interfaces based on concurrent checking","authors":"M. Nicolaidis","doi":"10.1109/ATS.1994.367255","DOIUrl":"https://doi.org/10.1109/ATS.1994.367255","url":null,"abstract":"This paper presents a strongly fail safe interface which transforms binary signals, generated by a system with error detection capabilities and eventually with fault tolerant capabilities, into fail safe signals. That is to say into signals which in the presence of failures will be either correct or safe. The strongly fail-safe property is achieved by means of concurrent checking techniques. The interest of this interface is that it can be implemented in VLSI, while the conventional fail-safe interfaces require to use discrete components.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient techniques for multiple fault test generation 有效的多故障测试生成技术
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367254
S. Kajihara, Rikiya Nishigaya, T. Sumioka, K. Kinoshita
{"title":"Efficient techniques for multiple fault test generation","authors":"S. Kajihara, Rikiya Nishigaya, T. Sumioka, K. Kinoshita","doi":"10.1109/ATS.1994.367254","DOIUrl":"https://doi.org/10.1109/ATS.1994.367254","url":null,"abstract":"This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125691653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
On full path delay fault testability of combinational circuits 组合电路全径延时故障可测性研究
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367213
Xiaodong Xie, A. Albicki
{"title":"On full path delay fault testability of combinational circuits","authors":"Xiaodong Xie, A. Albicki","doi":"10.1109/ATS.1994.367213","DOIUrl":"https://doi.org/10.1109/ATS.1994.367213","url":null,"abstract":"We show that robust tests for all path delay faults in a combinational circuit are not necessary in order to avoid test invalidation due to undesired hazards. Further extension leads to the formulation of the necessary and sufficient conditions for any path delay fault in a multi-level combinational circuit to be testable without potential invalidation by undesired hazards. We prove that all algebraic transformations and constrained resubstitution with complement are testability-preserving for the tests chosen.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129956658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On crosstalk fault detection in hierarchical VLSI logic circuits 层次VLSI逻辑电路串扰故障检测研究
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367234
A. Liaud, J. Fourniols, E. Sicard
{"title":"On crosstalk fault detection in hierarchical VLSI logic circuits","authors":"A. Liaud, J. Fourniols, E. Sicard","doi":"10.1109/ATS.1994.367234","DOIUrl":"https://doi.org/10.1109/ATS.1994.367234","url":null,"abstract":"A realistic crosstalk fault detector operating at hierarchical layout and logic level is presented. A set of filtering schemes are proposed to reduce considerably the set of probable single and multiple coupling faults with details on substrate resistivity and unbalanced buffer implications. Comparisons between flat and hierarchical layout approaches are reported together with the performances of the tool for various IC implementations.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130964928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An approach of diagnosing single bridging faults in CMOS combinational circuits CMOS组合电路中单桥故障的诊断方法
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367248
K. Yamazaki, T. Yamada
{"title":"An approach of diagnosing single bridging faults in CMOS combinational circuits","authors":"K. Yamazaki, T. Yamada","doi":"10.1109/ATS.1994.367248","DOIUrl":"https://doi.org/10.1109/ATS.1994.367248","url":null,"abstract":"An approach of diagnosing single bridging faults in CMOS combinational circuits is proposed. In this approach, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is proportional to [the number of gates]/spl times/[the number of tests], which is much smaller than that of the fault dictionary. The experimental results show that the CPU time is nearly proportional to the size of the circuit and the resolutions for most faults are less than 100, when using the tests to detect single stuck-at faults.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114255082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the performance analysis of parallel processing for test generation 测试生成并行处理的性能分析
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367251
T. Inoue, T. Fujii, H. Fujiwara
{"title":"On the performance analysis of parallel processing for test generation","authors":"T. Inoue, T. Fujii, H. Fujiwara","doi":"10.1109/ATS.1994.367251","DOIUrl":"https://doi.org/10.1109/ATS.1994.367251","url":null,"abstract":"The performance of parallel processing for test generation depends on the method of communication among processors. This paper presents two types of parallel processing which differ in communication methods, and analyzes their performance. We formulate the number of test vectors obtained in parallel processing, and analyze the costs of test generation, fault simulation and interprocessor communication and the speedup ratio. Further, we consider a method which minimizes the cost of interprocessor communication.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124670809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Sequential test generation in massive observability environments 大规模可观测环境下的顺序测试生成
Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI: 10.1109/ATS.1994.367243
P. Varma
{"title":"Sequential test generation in massive observability environments","authors":"P. Varma","doi":"10.1109/ATS.1994.367243","DOIUrl":"https://doi.org/10.1109/ATS.1994.367243","url":null,"abstract":"This paper describes a sequential test generation method for circuits in massive observability environments such as those offered by quiescent current monitoring and gate arrays with embedded test points. Techniques to enhance the controllability of the circuit are also discussed and an algorithm for selecting storage elements to make accessible during the test mode is proposed.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121152227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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