有效的多故障测试生成技术

Proceedings of IEEE 3rd Asian Test Symposium (ATS) Pub Date : 1994-11-15 DOI:10.1109/ATS.1994.367254

S. Kajihara, Rikiya Nishigaya, T. Sumioka, K. Kinoshita

{"title":"有效的多故障测试生成技术","authors":"S. Kajihara, Rikiya Nishigaya, T. Sumioka, K. Kinoshita","doi":"10.1109/ATS.1994.367254","DOIUrl":null,"url":null,"abstract":"This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques.<<ETX>>","PeriodicalId":182440,"journal":{"name":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"Efficient techniques for multiple fault test generation\",\"authors\":\"S. Kajihara, Rikiya Nishigaya, T. Sumioka, K. Kinoshita\",\"doi\":\"10.1109/ATS.1994.367254\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques.<<ETX>>\",\"PeriodicalId\":182440,\"journal\":{\"name\":\"Proceedings of IEEE 3rd Asian Test Symposium (ATS)\",\"volume\":\"201 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE 3rd Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1994.367254\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE 3rd Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1994.367254","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 15

摘要

本文介绍了基于并行向量对分析的多卡滞故障组合测试生成技术。该技术加速了测试的生成，减少了生成的测试向量的数量，同时获得了更高的故障覆盖率。基准电路的实验结果表明了该方法的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Efficient techniques for multiple fault test generation

This paper presents techniques used in combinational test generation for multiple stuck-at faults using the parallel vector pair analysis. The techniques accelerate test generation and reduce the number of test vectors generated, while higher fault coverage is derived. Experimental result for benchmark circuits shows the effectiveness of using the techniques.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

自引率

0.00%

发文量